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| INTEGRATED CIRCUITS DATA SHEET SAA7114H PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Preliminary specification File under Integrated Circuits, IC22 2000 Mar 15 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC SAA7114H comb filter, VBI-data slicer and high performance scaler CONTENTS 1 1.1 1.2 1.3 1.4 1.5 1.6 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 FEATURES Video decoder Video scaler Vertical Blanking Interval (VBI) data decoder and slicer Audio clock generation Digital I/O interfaces Miscellaneous APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Decoder Decoder output formatter Scaler VBI-data decoder and capture (subaddresses 40H to 7FH) Image port output formatter (subaddresses 84H to 87H) Audio clock generation (subaddresses 30H to 3FH) INPUT/OUTPUT INTERFACES AND PORTS Analog terminals Audio clock signals Clock and real-time synchronization signals Video expansion port (X-port) Image port (I-port) Host port for 16-bit extension of video data I/O (H-port) Basic input and output timing diagrams I-port and X-port 16 16.1 16.2 16.3 16.4 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 10 10.1 10.2 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION INFORMATION I2C-BUS DESCRIPTION I2C-bus format I2C-bus details Programming register audio clock generation Programming register VBI-data slicer Programming register interfaces and scaler part PROGRAMMING START SET-UP Decoder part Audio clock generation part Data slicer and data type control part Scaler and interfaces PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS 2000 Mar 15 2 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 1 1.1 FEATURES Video decoder SAA7114H * Six analog inputs, internal analog source selectors, e.g. 6 x CVBS or (2 x Y/C and 2 x CVBS) or (1 x Y/C and 4 x CVBS) * Two analog preprocessing channels in differential CMOS style inclusive built-in analog anti-alias filters * Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel * Automatic Clamp Control (ACC) for CVBS, Y and C * Switchable white peak control * Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or Y/C signals are available on the expansion port * On-chip line-locked clock generation according "ITU 601" * Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR * Requires only one crystal (32.11 or 24.576 MHz) for all standards * Horizontal and vertical sync detection * Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards * Luminance and chrominance signal processing for PAL BGDHIN, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM * Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation - Increased luminance and chrominance bandwidth for all PAL and NTSC standards - Reduced cross colour and cross luminance artefacts * PAL delay line for correcting PAL phase errors * Independent Brightness Contrast Saturation (BCS) adjustment for decoder part * User programmable sharpness control * Independent gain and offset adjustment for raw data path. 1.2 Video scaler * Horizontal and vertical down-scaling and up-scaling to randomly sized windows * Horizontal and vertical scaling range: variable zoom to 1 (icon); it should be noted that the H and V zoom are 64 restricted by the transfer data rates * Anti-alias and accumulating filter for horizontal scaling * Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy) * Horizontal phase correct up and down scaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width) * Two independent programming sets for scaler part, to define two `ranges' per field or sequences over frames * Fieldwise switching between decoder part and expansion port (X-port) input * Brightness, contrast and saturation controls for scaled outputs. 1.3 Vertical Blanking Interval (VBI) data decoder and slicer * Versatile VBI-data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North-American Broadcast Text System (NABTS), close caption, Wide Screen Signalling (WSS) etc. 1.4 Audio clock generation * Generation of a field locked audio master clock to support a constant number of audio clocks per video field * Generation of an audio serial and left/right (channel) clock signal. 2000 Mar 15 3 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 1.5 Digital I/O interfaces 3 GENERAL DESCRIPTION SAA7114H * Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to external document "RTC Functional Specification" for details) * Bi-directional expansion port (X-port) with half duplex functionality (D1), 8-bit YUV - Output from decoder part, real-time and unscaled - Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible) * Video image port (I-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and hand shake signals * Discontinuous data streams supported * 32-word x 4-byte FIFO register for video output data * 28-word x 4-byte FIFO register for decoded VBI output data * Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 YUV output * Scaled 8-bit luminance only and raw CVBS data output * Sliced, decoded VBI-data output. 1.6 Miscellaneous The SAA7114H is a video capture device for applications at the image port of VGA controllers. The SAA7114H is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and down scaling and a brightness, contrast and saturation control circuit. It is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7114H accepts as analog inputs CVBS or S-video (Y/C) from TV or VCR sources, including weak and distorted signals. An expansion port (X-port) for digital video (bi-directional half duplex, D1 compatible) is also supported to connect to MPEG or video phone codec. At the so called image port (I-port) the SAA7114H supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers. The target application for SAA7114H is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for display via VGA's frame buffer, or for capture to system memory. In parallel SAA7114H incorporates also provisions for capturing the serially coded data in the vertical blanking interval (VBI-data). Two principal functions are available: 1. To capture raw video samples, after interpolation to the required output data rate, via the scaler 2. A versatile data slicer (data recovery) unit. * Power-on control * 5 V tolerant digital inputs and I/O ports * Software controlled power saving standby modes supported * Programming via serial I2C-bus, full read-back ability by an external controller, bit rate up to 400 kbits/s * Boundary scan test circuit complies with the "IEEE Std. 1149.b1 - 1994". 2 APPLICATIONS * Desktop video * Multimedia * Digital television * Image processing * Video phone applications. SAA7114H incorporates also a field locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio, during capture or playback. The circuit is I2C-bus controlled (full write/read capability for all programming registers, bit rate up to 400 kbits/s). 2000 Mar 15 4 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 4 QUICK REFERENCE DATA SYMBOL VDDD VDDDC VDDA Tamb PA+D Note PARAMETER digital supply voltage digital core supply voltage analog supply voltage operating ambient temperature analog and digital power dissipation; note 1 3.0 3.0 3.1 0 - MIN. 3.3 3.3 3.3 - 0.45 TYP. 3.6 3.6 3.5 70 - SAA7114H MAX. V V V C W UNIT 1. Power dissipation is measured in CVBS input mode (only one ADC active) and 8-bit image port output mode, expansion port is 3-stated. 5 ORDERING INFORMATION TYPE NUMBER SAA7114H PACKAGE NAME LQFP100 DESCRIPTION plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm VERSION SOT407-1 2000 Mar 15 5 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ull pagewidth AI12 AI21 AI22 AI23 16 14 12 10 22 19 13 21 ANALOG DUAL ADC AI24 AOUT AI1D AI2D AGND DIGITAL DECODER WITH ADAPTIVE COMB FILTER EVENT CONTROLLER IMAGE PORT PIN MAPPING 2000 Mar 15 LLC RES CE XTOUT XTALI XTALO AI11 30 27 4 7 6 20 18 6 Philips Semiconductors PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler BLOCK DIAGRAM LLC2 RTS0 (1) XCLK XPD [7:0] XRH 81, 82, 84 to 87 89, 90 92 XRV XTRI HPD [7:0] 80 64 to 67, 69 to 72 I/O CONTROL SDA 32 SCL 31 TEST5 TEST3 TEST1 TEST0 73 44 RTCO 29 36 RTS1 34 35 94 XDQ 95 XRDY 91 96 TEST4 79 78 TEST2 77 74 28 REAL-TIME OUTPUT EXPANSION PORT PIN MAPPING I2C-BUS X PORT I/O FORMATTING CLOCK GENERATION AND POWER-ON CONTROL chrominance of 16-bit input SAA7114H PROGRAMMING REGISTER ARRAY A/B REGISTER MUX 54 to 57, 59 to 62 46 53 52 48 49 IPD [7:0] IDQ IGPH IGPV IGP0 IGP1 FIR-PREFILTER HORIZONTAL LINE VERTICAL PRESCALER FINE FIFO SCALING AND (PHASE) BUFFER SCALER BCS SCALING VIDEO FIFO 6 BOUNDARY SCAN TEST AUDIO CLOCK GENERATION GENERAL PURPOSE VBI-DATA SLICER TEXT FIFO 32 to 8(16) MUX 45 ICLK 42 VIDEO/TEXT ARBITER 47 ITRDY ITRI 97 98 99 3 TCK TRST TDI 2 37 40 39 41 8 5 33, 43, 58, 68, 83, 93 1, 25, 51, 75 23, 17, 11 38, 63, 88 26, 50, 76, 100 24, 15, 9 MHB528 AMCLK TMS TDO ASCLK VDD(XTAL) VDDD(ICO1) to ALRCLK AMXCLK VDDD(ICO6) (1) VDDA0 to VDDA2 VSSD(EP1) to VSSD(EP4) VSSD(ICO1) to VSSD(ICO3) VSSA0 to VSSA2 VSS(XTAL) VDDD(EP1) to VDDD(EP4) Preliminary specification SAA7114H (1) The pins RTCO and ALRCLK are used for configuration of the I2C-bus interface and the definition of the crystal oscillator frequency at RESET (pin strapping). Fig.1 Block diagram. Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 7 PINNING SYMBOL VDDD(EP1) TDO TDI XTOUT VSS(XTAL) XTALO XTALI VDD(XTAL) VSSA2 AI24 VDDA2 AI23 AI2D AI22 VSSA1 AI21 VDDA1 AI12 AI1D AI11 AGND AOUT VDDA0 VSSA0 VDDD(EP2) VSSD(EP1) CE LLC LLC2 RES SCL SDA VDDD(ICO1) RTS0 RTS1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 TYPE P O I O P O I P P I P I I I P I P I I I P O P P P P I O O O I(/O) I/O P O O DESCRIPTION external digital pad supply voltage 1 (+3.3 V) test data output for boundary scan test; note 1 test data input for boundary scan test; note 1 crystal oscillator output signal; auxiliary signal ground for crystal oscillator SAA7114H 24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL clock input of XTALI is used input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of external oscillator with TTL compatible square wave clock signal supply voltage for crystal oscillator ground for analog inputs AI2n analog input 24 analog supply voltage for analog inputs AI2n (+3.3 V) analog input 23 differential input for ADC channel 2 (pins AI24, AI23, AI22 and AI21) analog input 22 ground for analog inputs AI1n analog input 21 analog supply voltage for analog inputs AI1n (+3.3 V) analog input 12 differential input for ADC channel 1 (pins AI12 and AI11) analog input 11 analog ground connection do not connect; analog test output analog supply voltage (+3.3 V) for internal Clock Generation Circuit (CGC) ground for internal clock generation circuit external digital pad supply voltage 2 (+3.3 V) external digital pad supply ground 1 chip enable or reset input (with internal pull-up) line-locked system clock output (27 MHz nominal) line-locked 12 clock output (13.5 MHz nominal) reset output (active LOW) serial clock input (I2C-bus) with inactive output path serial data input/output (I2C-bus) internal digital core supply voltage 1 (+3.3 V) real-time status or sync information, controlled by subaddresses 11H and 12H; see Section 15.2.18, 15.2.19 and 15.2.20 2000 Mar 15 7 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SYMBOL RTCO PIN 36 TYPE (I/)O DESCRIPTION SAA7114H real-time control output; contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see external document "RTC Functional Description", available on request); the RTCO pin is enabled via I2C-bus bit RTCE; see notes 2, 3 and Table 34 audio master clock output, up to 50% of crystal clock internal digital core supply ground 1 audio serial clock output audio left/right clock output; can be strapped to supply via a 3.3 k resistor to indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down) has been replaced by a 32.110 MHz crystal (ALRCLK = 1); see notes 2 and 4 audio master external clock input target ready input, image port (with internal pull-up) internal digital core supply voltage 2 (+3.3 V) do not connect; reserved for future extensions and for testing: scan output clock output signal for image port, or optional asynchronous back-end clock input output data qualifier for image port (optional: gated clock output) image port output control signal, effects all input port pins inclusive ICLK, enable and active polarity is under software control (bits IPE in subaddress 87H); output path used for testing: scan output general purpose output signal 0; image port (controlled by subaddresses 84H and 85H) general purpose output signal 1; image port (controlled by subaddresses 84H and 85H) external digital pad supply ground 2 external digital pad supply voltage 3 (+3.3 V) multi purpose vertical reference output signal; image port (controlled by subaddresses 84H and 85H) multi purpose horizontal reference output signal; image port (controlled by subaddresses 84H and 85H) image port data outputs internal digital core supply voltage 3 (+3.3 V) image port data output internal digital core supply ground 2 host port data I/O, carries UV chrominance information in 16-bit video I/O modes internal digital core supply voltage 4 (+3.3 V) host port data I/O, carries UV chrominance information in 16-bit video I/O modes do not connect; reserved for future extensions and for testing: scan input do not connect; reserved for future extensions and for testing: scan input external digital pad supply voltage 4 (+3.3 V) external digital pad supply ground 3 do not connect; reserved for future extensions and for testing: scan input AMCLK VSSD(ICO1) ASCLK ALRCLK 37 38 39 40 O P O (I/)O AMXCLK ITRDY VDDD(ICO2) TEST0 ICLK IDQ ITRI 41 42 43 44 45 46 47 I I P O I/O O I(/O) IGP0 IGP1 VSSD(EP2) VDDD(EP3) IGPV IGPH IPD7 to IPD4 VDDD(ICO3) IPD3 to IPD0 VSSD(ICO2) HPD7 to HPD4 VDDD(ICO4) HPD3 to HPD0 TEST1 TEST2 VDDD(EP4) VSSD(EP3) TEST3 48 49 50 51 52 53 54 to 57 58 59 to 62 63 64 to 67 68 69 to 72 73 74 75 76 77 O O P P O O O P O P I/O P I/O I I P P I 2000 Mar 15 8 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SYMBOL TEST4 TEST5 XTRI PIN 78 79 80 TYPE O I I DESCRIPTION SAA7114H do not connect; reserved for future extensions and for testing: scan output do not connect; reserved for future extensions and for testing: scan input X-port output control signal, affects all X-port pins (XPD7 to XPD0, XRH, XRV, XDQ and XCLK), enable and active polarity is under software control (bits XPE in subaddress 83H) expansion port data expansion port data internal digital core supply voltage 5 (+3.3 V) expansion port data internal digital core supply ground 3 expansion port data expansion port data vertical reference I/O expansion port horizontal reference I/O expansion port internal digital core supply voltage 6 (+3.3 V) clock I/O expansion port data qualifier I/O expansion port task flag or ready signal from scaler, controlled by XRQT test reset input (active LOW), for boundary scan test (with internal pull-up); notes 5 and 6 test clock for boundary scan test; note 1 test mode select input for boundary scan test or scan test; note 1 external digital pad supply ground 4 XPD7 XPD6 VDDD(ICO5) XPD5 to XPD2 VSSD(ICO3) XPD1 XPD0 XRV XRH VDDD(ICO6) XCLK XDQ XRDY TRST TCK TMS VSSD(EP4) Notes 81 82 83 84 to 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O I/O P I/O P I/O I/O I/O I/O P I/O I/O O I I I P 1. In accordance with the "IEEE1149.1" standard the pads TDI, TMS, TCK and TRST are input pads with an internal pull-up transistor and TDO is a 3-state output pad. 2. Pin strapping is done by connecting the pin to supply via a 3.3 k resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down). 3. Pin RTCO: operates as I2C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave address 40H/41H. 4. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal. 5. For board design without boundary scan implementation connect the TRST pin to ground. 6. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. 2000 Mar 15 9 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H 93 VDDD(ICO6) 100 VSSD(EP4) 83 VDDD(ICO5) 88 VSSD(ICO3) 79 TEST5 78 TEST4 VDDD(EP1) TDO TDI XTOUT VSS(XTAL) XTALO XTALI VDD(XTAL) VSSA2 77 TEST3 handbook, full pagewidth 76 VSSD(EP3) 75 VDDD(EP4) 74 TEST2 73 TEST1 72 HPD0 71 HPD1 70 HPD2 69 HPD3 68 VDDD(ICO4) 67 HPD4 66 HPD5 65 HPD6 64 HPD7 63 VSSD(ICO2) 62 IPD0 61 IPD1 60 IPD2 59 IPD3 58 VDDD(ICO3) 57 IPD4 56 IPD5 55 IPD6 54 IPD7 53 IGPH 52 IGPV 51 VDDD(EP3) 96 XRDY 94 XCLK 90 XPD0 89 XPD1 87 XPD2 86 XPD3 85 XPD4 84 XPD5 82 XPD6 81 XPD7 ICLK 45 97 TRST 1 2 3 4 5 6 7 8 9 AI24 10 VDDA2 11 AI23 12 AI2D 13 AI22 14 VSSA1 15 AI21 16 VDDA1 17 AI12 18 AI1D 19 AI11 20 AGND 21 AOUT 22 VDDA0 23 VSSA0 24 VDDD(EP2) 25 SAA7114H VSSD(EP1) 26 CE 27 LLC 28 LLC2 29 RES 30 SCL 31 SDA 32 VDDD(ICO1) 33 RTS0 34 RTS1 35 RTCO 36 AMCLK 37 VSSD(ICO1) 38 ASCLK 39 ALRCLK 40 AMXCLK 41 ITRDY 42 VDDD(ICO2) 43 TEST0 44 IDQ 46 80 XTRI 95 XDQ 99 TMS 92 XRH 91 XRV 98 TCK ITRI 47 IGP0 48 IGP1 49 VSSD(EP2) 50 MHB529 Fig.2 Pin configuration. 2000 Mar 15 10 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 1 8-bit/16-bit and alternative pin functional configurations 2000 Mar 15 11 92 XRH 91 XRV 80 XTRI 64 to 67, 69 to 72 HPD7 to HPD0 Philips Semiconductors PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler PIN SYMBOL 8-BIT INPUT MODES D1 data input clock input 16-BIT INPUT MODES (ONLY FOR I2C-BUS PROGRAMMING) Y data input ALTERNATIVE INPUT FUNCTIONS 8-BIT OUTPUT MODES D1 decoder output 16-BIT OUTPUT MODES (ONLY FOR I2C-BUS PROGRAMMING) ALTERNATIVE OUTPUT FUNCTIONS I/O CONFIGURATION PROGRAMMING BITS XCODE[92H[3]] XPE[1:0]83H[1:0] + pin XTRI XPE[1:0]83H[1:0] + pin XTRI XPCK[1:0]83H[5:4] XCKS[92H[0]] XDQ[92H[1]] XPE[1:0]83H[1:0] + pin XTRI 81, 82, 84 to 87, 89, 90 94 XPD7 to XPD0 XCLK gated clock input decoder clock output data qualifier output (HREF and VREF gate) 95 XDQ data qualifier input 96 XRDY input ready output horizontal reference input vertical reference input output enable input UV data input active task A/B flag decoder horizontal reference output decoder vertical reference output XRQT[83H[2]] XPE[1:0]83H[1:0] + pin XTRI XDH[92H[2]] XPE[1:0]83H[1:0] + pin XTRI XDV[1:0]92H[5:4] XPE[1:0]83H[1:0] + pin XTRI XPE[1:0]83H[1:0] Preliminary specification UV scaler output ICODE[93H[7]] ISWP[1:0]85H[7:6] I8_16[93H[6]] IPE[1:0]87H[1:0] + pin ITRI SAA7114H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Mar 15 45 46 42 53 12 52 49 48 47 Philips Semiconductors 8-BIT INPUT MODES 16-BIT INPUT MODES (ONLY FOR I2C-BUS PROGRAMMING) ALTERNATIVE INPUT FUNCTIONS 8-BIT OUTPUT MODES D1 scaler output 16-BIT OUTPUT MODES (ONLY FOR I2C-BUS PROGRAMMING) Y scaler output ALTERNATIVE OUTPUT FUNCTIONS I/O CONFIGURATION PROGRAMMING BITS ICODE[93H[7]] ISWP[1:0]85H[7:6] I8_16[93H[6]] IPE[1:0]87H[1:0] + pin ITRI clock input ICKS[1:0]80H[1:0] IPE[1:0]87H[1:0] + pin ITRI ICKS[3:2]80H[3:2] IDQP[85H[0]] IPE[1:0]87H[1:0] + pin ITRI PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler PIN SYMBOL 54 to 57, 59 to 62 IPD7 to IPD0 ICLK clock output data qualifier output target ready input H-gate output IDQ gated clock output ITRDY IGPH extended H-gate, horizontal pulses V-sync, vertical pulses IDH[1:0]84H[1:0] IRHP[85H[1]] IPE[1:0]87H[1:0] + pin ITRI IDV[1:0]84H[3:2] IRVP[85H[2]] IPE[1:0]87H[1:0] + pin ITRI IDG1[1:0]84H[5:4] IG1P[85H[3]] IPE[1:0]87H[1:0] + pin ITRI IDG0[1:0]84H[7:6] IG0P[85H[4]] IPE[1:0]87H[1:0] + pin ITRI IGPV V-gate output IGP1 general purpose IGP0 general purpose Preliminary specification SAA7114H ITRI output enable input Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8 8.1 8.1.1 FUNCTIONAL DESCRIPTION Decoder ANALOG INPUT PROCESSING 8.1.2 ANALOG CONTROL CIRCUITS SAA7114H The SAA7114H offers six analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Fig.6. The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristics are shown in Fig.3. During the vertical blanking period, gain and clamping control are frozen. MGD138 handbook, full pagewidth 6 V (dB) 0 -6 -12 -18 -24 -30 -36 -42 0 2 4 6 8 10 12 f (MHz) 14 Fig.3 Anti-alias filter. 2000 Mar 15 13 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.1.2.1 Clamping SAA7114H The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal. The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. The AGC active time is the sync bottom of the video signal. Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figs 7 and 8) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control. 8.1.2.2 Gain control The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers or controls one of these amplifiers automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input Control (AICO). handbook, halfpage TV line analog line blanking handbook, halfpage analog input level +3 dB maximum controlled ADC input level 255 GAIN 60 1 CLAMP 0 dB (1 V (p-p) 18/56 ) -6 dB range 9 dB 0 dB minimum MHB325 HCL HSY MGL065 Fig.4 Analog line with clamp (HCL) and gain range (HSY). Fig.5 Automatic gain range. 2000 Mar 15 14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ndbook, full pagewidth 2000 Mar 15 VSSA1 VSSA2 AI2D AI24 to AI21 VDDA1 VDDA2 AI12 AI1D AI11 15 9 13 10, 12, 14, 16 17 11 18 19 20 SOURCE SWITCH CLAMP CIRCUIT ANALOG AMPLIFIER DAC9 SOURCE SWITCH CLAMP CIRCUIT ANALOG AMPLIFIER DAC9 Philips Semiconductors PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler TEST SELECTOR AND BUFFER AOSL [1:0] 22 AOUT ANTI-ALIAS FILTER BYPASS SWITCH ADC2 FUSE [1:0] ANTI-ALIAS FILTER BYPASS SWITCH ADC1 FUSE [1:0] 15 MODE CONTROL CLAMP CONTROL GAIN CONTROL ANTI-ALIAS CONTROL VERTICAL BLANKING CONTROL MODE 3 MODE 2 MODE 1 MODE 0 HCL GLIMB HSY GLIMT WIPA SLTCA HOLDG GAFIX WPOFF GUDL0-GUDL2 GAI20-GAI28 GAI10-GAI18 HLNRS UPTCV VBSL VBLNK SVREF 9 9 ANALOG CONTROL AGND 21 9 CVBS/LUM 9 CVBS/CHR Preliminary specification CROSS MULTIPLEXER 9 9 MHB530 SAA7114H AD2BYP AD1BYP Fig.6 Analog input processing using the SAA7114H as differential front-end with 9-bit ADC. Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER ADC 9 LUMA/CHROMA DECODER gain DAC 9 NO ACTION 1 VBLK 1 0 0 0 1 0 HOLDG 1 X HSY 0 0 1 > 254 1 1 0 1 0 <4 <1 > 254 X=0 1 > 248 0 X=1 +1/F STOP +1/L -1/LLC2 +1/LLC2 -1/LLC2 +/- 0 GAIN ACCUMULATOR (18 BITS) ACTUAL GAIN VALUE 9-BIT (AGV) [-3/+6 dB] 1 0 1 X HSY 1 0 0 Y AGV UPDATE FGV GAIN VALUE 9-BIT MHB531 X = system variable. Y = (IAGV - FGVI) > GUDL. VBLK = vertical blanking pulse. HSY = horizontal sync pulse. AGV = actual gain value. FGV = frozen gain value. Fig.7 Gain flow chart. 2000 Mar 15 16 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth ANALOG INPUT ADC NO BLANKING ACTIVE 1 VBLK 0 <- CLAMP GAIN -> 1 HCL 0 1 HSY 0 1 CLL 0 0 SBOT 1 1 WIPE 0 + CLAMP - CLAMP NO CLAMP + GAIN - GAIN fast - GAIN slow + GAIN MGC647 WIPE = white peak level (254). SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse. Fig.8 Clamp and gain flow chart. 2000 Mar 15 17 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ndbook, full pagewidth 2000 Mar 15 CVBS-IN or Y-IN LDEL YCOMB DELAY COMPENSATION CHR QUADRATURE MODULATOR UV LUBW CVBS-IN or CHR-IN QUADRATURE DEMODULATOR LOW-PASS 1 DOWNSAMPLING SUBCARRIER GENERATION 2 LCBW [ 2:0] 8.1.3 CHROMINANCE AND LUMINANCE PROCESSING Philips Semiconductors PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Y SUBTRACTOR LUMINANCE-PEAKING OR LOW-PASS, Y-DELAY ADJUSTMENT Y/CVBS DBRI [ 7:0] DCON [ 7:0] DSAT [ 7:0] RAWG [ 7:0] RAWO [ 7:0] COLO INTERPOLATION LOW-PASS 3 LUFI [ 3:0] CSTD [ 2:0] YDEL [ 2:0] SET_RAW SET_VBI UV ADAPTIVE COMB FILTER UV LOW-PASS 2 BRIGHTNESS CONTRAST SATURATION CONTROL RAW DATA GAIN AND OFFSET CONTROL Y-OUT/ CVBS OUT UV-OUT SET_RAW CCOMB SET_VBI YCOMB LDEL BYPS CHBW HREF-OUT CHROMINANCE INCREMENT DELAY LDEL YCOMB SECAM PROCESSING 18 SUBCARRIER GENERATION 1 HUEC UV CHROMINANCE INCREMENT DTO-RESET SUBCARRIER INCREMENT GENERATION AND DIVIDER PHASE DEMODULATOR AMPLITUDE DETECTOR BURST GATE ACCUMULATOR LOOP FILTER SET_RAW SET_VBI CHROMA GAIN CONTROL PAL DELAY LINE UVADJUSTMENT SECAM RECOMBINATION CDTO INCS CSTD [ 2:0] RTCO FCTC ACGC CGAIN [ 6:0] IDEL [ 3:0] CODE SECS SET_RAW SET_VBI DCVF Preliminary specification MHB532 fH /2 switch signal SAA7114H Fig.9 Chrominance and luminance processing. Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.1.3.1 Chrominance path SAA7114H The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0 and 90 phase relationship to the demodulator axis). The frequency is dependent on the chosen colour standard. The time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). Eight characteristics are programmable via LCWB3 to LCWB0 to achieve the desired bandwidth for the colour difference signals (PAL, NTSC) or the 0 and 90 FM signals (SECAM). The chrominance low-pass 1 characteristic also influences the grade of cross-luminance reduction during horizontal colour transients (large chrominance bandwidth means strong suppression of cross-luminance). If the Y-comb filter is disabled by YCOMB = 0 the filter influences directly the width of the chrominance notch within the luminance path (large chrominance bandwidth means wide chrominance notch resulting to lower luminance bandwidth). The low-pass filtered signals are fed to the adaptive comb filter block. The chrominance components are separated from the luminance via a two line vertical stage (four lines for PAL standards) and a decision logic between the filtered and the non-filtered output signals. This block is bypassed for SECAM signals. The comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by YCOMB (subaddress 09H, bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always bypassed during VBI or raw data lines programmable by the LCRn registers (subaddresses 41H to 57H), see Section 8.2. The separated UV-components are further processed by a second filter stage (low-pass 2) to modify the chrominance bandwidth without influence to the luminance path. It's characteristic is controlled by CHBW (subaddress 10H, bit 3). For the complete transfer characteristic of low-passes 1 and 2 see Figs 10 and 11. The SECAM processing (bypassed for QUAM standards) contains the following blocks: * Baseband `bell' filters to reconstruct the amplitude and phase equalized 0 and 90 FM signals * Phase demodulator and differentiator (FM-demodulation) * De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal). 2000 Mar 15 19 The succeeding chrominance gain control block amplifies or attenuates the UV-signal according to the required ITU 601/656 levels. It is controlled by the output signal from the amplitude detection circuit within the burst processing block. The burst processing block provides the feedback loop of the chrominance PLL and contains: * Burst gate accumulator * Colour identification and killer * Comparison nominal/actual burst amplitude (PAL/NTSC standards only) * Loop filter chrominance gain control (PAL/NTSC standards only) * Loop filter chrominance PLL (only active for PAL/NTSC standards) * PAL/SECAM sequence detection, H/2-switch generation. The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals). The PAL delay line block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards the delay line can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1. It is always disabled during VBI or raw data lines programmable by the LCRn registers (subaddresses 41H to 47H), see Section 8.2. The embedded line delay is also used for SECAM recombination (cross-over switches). Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) MHB533 V (dB) (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) (5) (6) (7) (8) Fig.10 Transfer characteristics of the chrominance low-pass at CHBW = 0. 2000 Mar 15 20 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) MHB534 V (dB) (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) (5) (6) (7) (8) Fig.11 Transfer characteristics of the chrominance low-pass at CHBW = 1. 2000 Mar 15 21 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.1.3.2 Luminance path SAA7114H The rejection of the chrominance components within the 9-bit CVBS or Y input signal is done by subtracting the re-modulated chrominance signal from the CVBS input. The comb filtered UV-components are interpolated (upsampled) by the low-pass 3 block. It's characteristic is controlled by LUBW (subaddress 09H, bit 4) to modify the width of the chrominance `notch' without influence to the chrominance path. The programmable frequency characteristics available in conjunction with the LCBW2 to LCBW0 settings can be seen in Figs 12 to 15. Note that these frequency curves are only valid for Y-comb disabled filter mode (YCOMB = 0). in comb filter mode the frequency response is flat. The centre frequency of the notch is automatically adapted to the chosen colour standard. The interpolated UV-samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. This second DTO is locked to the first subcarrier generator by an increment delay circuit matched to the processing delay, which is different for PAL and NTSC standards according to the chosen comb filter algorithm. The two modulated signals are finally added to build the re-modulated chrominance signal. The frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. It can be configured as peaking (resolution enhancement) or low-pass block by LUFI3 to LUFI0 (subaddress 09H, bits 3 to 0). The 16 resulting frequency characteristics can be seen in Fig.16. The LUFI3 to LUFI0 settings can be used as a user programmable sharpness control. The luminance filter block also contains the adjustable Y-delay part; programmable by YDEL2 to YDEL0 (subaddress 11H, bits 2 to 0). 2000 Mar 15 22 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 -51 -54 -57 -60 (1) (2) (3) (4) MHB535 V (dB) (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) (5) (6) (7) (8) Fig.12 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW = 0. 2000 Mar 15 23 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) MHB536 V (dB) (1) (2) (3) (4) LCBW[2:0] = 000 LCBW[2:0] = 010 LCBW[2:0] = 100 LCBW[2:0] = 110 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (5) (6) (7) (8) LCBW[2:0] = 001 LCBW[2:0] = 011 LCBW[2:0] = 101 LCBW[2:0] = 111 -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) (5) (6) (7) (8) Fig.13 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW = 1. 2000 Mar 15 24 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) MHB537 V (dB) (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) (5) (6) (7) (8) Fig.14 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 0. 2000 Mar 15 25 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) MHB538 V (dB) (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) (5) (6) (7) (8) Fig.15 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 1. 2000 Mar 15 26 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth MHB539 9 8 (1) (2) V (dB) 7 6 5 4 3 (1) (2) (3) (4) (5) (6) (7) (8) LUFI[3:0] = 0001. LUFI[3:0] = 0010. LUFI[3:0] = 0011. LUFI[3:0] = 0100. LUFI[3:0] = 0101. LUFI[3:0] = 0110. LUFI[3:0] = 0111. LUFI[3:0] = 0000. 2 1 0 -1 0 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 (9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111. -24 -27 -30 -33 -36 -39 0 0.5 1.0 0.5 1.0 (3) (4) (5) (6) (7) (8) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 f (MHz) 6.0 (9) (10) (11) (12) (13) (14) (15) (16) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 f (MHz) 6.0 Fig.16 Transfer characteristics of the luminance peaking/low-pass filter (sharpness). 2000 Mar 15 27 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.1.3.3 Brightness Contrast Saturation (BCS) control and decoder output levels SAA7114H The resulting Y (CVBS) and UV-signals are fed to the BCS block, which contains the following functions: * Chrominance saturation control by DSAT7 to DSAT0 * Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0 * Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0 * Limiting YUV or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil "ITU Recommendation 601/656". ndbook, full pagewidth +255 +235 white +255 +240 +212 blue 100% blue 75% +255 +240 +212 red 100% red 75% +128 LUMINANCE 100% +128 U-COMPONENT colourless +128 V-COMPONENT colourless +44 +16 0 black +16 0 yellow 75% yellow 100% +44 +16 0 cyan 75% cyan 100% MGC634 a. Y output range. b. U output range (CB). c. V output range (CR). "ITU Recommendation 601/656" digital levels with default BCS (decoder) settings DCON[7:0] = 44H, DBRI[7:0] = 80H and DSAT[7:0] = 40H. Equations for modification to the YUV levels via BCS control I2C-bus bytes DBRI, DCON and DSAT. Luminance: DCON Y OUT = Int ---------------- x ( Y - 128 ) + DBRI 68 DSAT Chrominance: UV OUT = Int --------------- x ( C R, C B - 128 ) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with "ITU Recommendation 601/656" . Fig.17 YUV range for scaler input and X-port output. 2000 Mar 15 28 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth +255 +209 white +255 +199 white LUMINANCE LUMINANCE +71 +60 SYNC 1 black black shoulder +60 SYNC black shoulder = black sync bottom 1 sync bottom MGD700 a. Sources containing 7.5 IRE black level offset (e.g. NTSC M). b. Sources not containing black level offset. CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128. Equation for modification of the raw data levels via bytes RAWG and RAWO: RAWG CVBS OUT = Int ----------------- x ( CVBS nom - 128 ) + RAWO 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with "ITU Recommendation 601/656". Fig.18 CVBS (raw data) range for scaler input, data slicer and X-port output. 2000 Mar 15 29 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.1.4 SYNCHRONIZATION SAA7114H The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO, see Fig.19. The detection of `pseudo syncs' as part of the macrovision copy protection standard is also done within the synchronization circuit. The result is reported as flag COPRO within the decoder status byte at subaddress 1FH. 8.1.5 CLOCK GENERATION CIRCUIT The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency: 6.75 MHz = 429 x fH (50 Hz), or 6.75 MHz = 432 x fH (60 Hz). Internally the LFCO signal is multiplied by a factor of 2 and 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50% duty factor. Table 2 Decoder clock frequencies CLOCK XTALO LLC LLC2 LLC4 (internal) LLC8 (virtual) FREQUENCY (MHz) 24.576 or 32.110 27 13.5 6.75 3.375 The internal CGC generates all clock signals required for the video input processor. handbook, full pagewidth LFCO BAND PASS FC = LLC/4 ZERO CROSS DETECTION PHASE DETECTION LOOP FILTER OSCILLATOR LLC DIVIDER 1/2 DIVIDER 1/2 MHB330 LLC2 Fig.19 Block diagram of the clock generation circuit. 8.1.6 POWER-ON RESET AND CHIP ENABLE (CE) INPUT A missing clock, insufficient digital or analog VDDA0 supply voltages (below 2.7 V) will start the reset sequence; all outputs are forced to 3-state (see Fig.20). The indicator output RES is LOW for about 128 LLC after the internal reset and can be applied to reset other circuits of the digital TV system. It is possible to force a reset by pulling the Chip Enable (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2 and SDA return from 3-state to active, while the other signals have to be activated via programming. 2000 Mar 15 30 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth POC V DDA ANALOG POC V DDD DIGITAL CLOCK PLL LLC CE POC LOGIC RESINT CLK0 POC DELAY RES CE XTALO LLCINT RESINT LLC RES (internal reset) some ms 20 to 200 s PLL-delay <1 ms 896 LCC digital delay 128 LCC MHB331 POC = Power-on Control. CE = chip enable input. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. LLC = line-locked clock output. RES = reset output Fig.20 Power-on control circuit. 2000 Mar 15 31 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.2 Decoder output formatter SAA7114H The output interface block of the decoder part contains the ITU 656 formatter for the expansion port data output XPD7 to XPD0 (for a detailed description see Section 9.4.1) and the control circuit for the signals needed for the internal paths to the scaler and data slicer part. It also controls the selection of the reference signals for the RT port (RTCO, RTS0 and RTS1) and the expansion port (XRH, XRV and XDQ). The generation of the decoder data type control signals SET_RAW and SET VBI is also done within this block. These signals are decoded from the requested data type for the scaler input and/or the data slicer, selectable by the control registers LCR2 to LCR24 (see also Chapter 15 "I2C-bus description", subaddresses 41H to 57H). Table 3 Data formats at decoder output DATA TYPE teletext EuroWST, CCST European closed caption For each LCR value from 2 to 23 the data type can be programmed individually. LCR2 to LCR23 refer to line numbers. The selection in LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0, located in subaddresses 5BH (bit 4) and 5AH (bits 7 to 0) and FOFF subaddress 5BH (bit D7). The recommended values are VOFF[8:0] = 03H for 50 Hz sources (with FOFF = 0) and VOFF[8:0] = 06H for 60 Hz sources (with FOFF = 1), to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Tables 4 to 7. DATA TYPE NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DECODER OUTPUT DATA FORMAT raw raw raw raw raw raw YUV 4 : 2 : 2 raw raw raw raw raw raw raw raw YUV 4 : 2 : 2 Video Programming Service (VPS) Wide screen signalling bits US teletext (WST) US closed caption (line 21) video component signal, VBI region CVBS data teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) video component signal, active video region 2000 Mar 15 32 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 4 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) LCR 521 259 522 260 523 active video 261 24 262 263 active video 524 525 1 264 2 265 2 3 266 3 4 267 4 5 serration pulses 268 5 269 6 serration pulses 6 7 270 7 8 271 8 9 272 9 equalization pulses equalization pulses equalization pulses equalization pulses 2000 Mar 15 33 Philips Semiconductors PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 5 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2) Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7]) Line number 10 (1st field) Line number (2nd field) LCR 273 10 11 274 11 12 275 12 13 276 13 14 277 14 15 278 15 16 279 16 17 280 17 18 281 18 19 282 19 20 283 20 21 284 21 22 285 22 23 286 23 24 287 24 25 288 nominal VBI-lines F1 nominal VBI-lines F2 active video active video Table 6 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1) Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) LCR 621 309 622 active video 310 311 24 active video 623 624 equalization pulses 312 313 314 serration pulses 2 3 equalization pulses 625 1 2 serration pulses 315 316 3 4 317 equalization pulses 4 5 5 318 equalization pulses Table 7 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) LCR 6 319 6 7 320 7 8 321 8 9 322 9 10 323 10 11 324 11 12 325 12 13 326 13 14 327 14 15 328 15 16 329 16 17 330 17 18 331 18 19 332 19 20 333 20 21 334 21 22 335 22 23 336 23 24 337 24 25 338 nominal VBI-lines F1 nominal VBI-lines F2 active video active video Preliminary specification SAA7114H Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth ITU counting single field counting CVBS 622 309 623 310 624 311 625 312 1 1 2 2 3 3 4 4 5 5 6 6 7 7 ... ... 22 22 23 23 HREF F_ITU656 V123 (1) VSTO [8:0] = 134H VGATE FID (a) 1st field VSTA [8:0] = 15H ITU counting single field counting CVBS 309 309 310 310 311 311 312 312 313 313 314 1 315 2 316 3 317 4 318 5 319 6 ... ... 335 22 336 23 HREF F_ITU656 V123 (1) VSTO [8:0] = 134H VGATE FID (b) 2nd field VSTA [8:0] = 15H MHB540 (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table: NAME HREF F_ITU656 V123 VGATE FID RTS0 (PIN 34) RTS1 (PIN 35) X - X X X X - X X X XRH (PIN 92) X - - - - XRV (PIN 91) X X - For further information see Section 15.2: Tables 55, 56 and 57. Fig.21 Vertical timing diagram for 50 Hz/625 line systems. 2000 Mar 15 34 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth ITU counting single field counting CVBS 525 262 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 ... ... 21 21 22 22 HREF F_ITU656 V123 (1) VSTO [8:0] = 101H VGATE FID (a) 1st field VSTA [8:0] = 011H ITU counting single field counting CVBS 262 262 263 263 264 1 265 2 266 3 267 4 268 5 269 6 270 7 271 8 272 9 ... ... 284 21 285 22 HREF F_ITU656 V123 (1) VSTO [8:0] = 101H VGATE FID (b) 2nd field VSTA [8:0] = 011H MHB541 (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table: NAME HREF F_ITU656 V123 VGATE FID RTS0 (PIN 34) RTS1 (PIN 35) X - X X X X - X X X XRH (PIN 92) X - - - - XRV (PIN 91) - X X - - For further information see Section 15.2: Tables 55, 56 and 57. Fig.22 Vertical timing diagram for 60 Hz/525 line systems. 2000 Mar 15 35 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth CVBS input burst processing delay ADC to expansion port: 140 x 1/LLC expansion port data output sync clipped HREF (50 Hz) 720 x 2/LLC CREF CREF2 5 x 2/LLC HS (50 Hz) programming range 108 (step size: 8/LLC) 0 2 x 2/LLC -107 12 x 2/LLC 144 x 2/LLC HREF (60 Hz) 16 x 2/LLC 720 x 2/LLC CREF CREF2 HS (60 Hz) programming range (step size: 8/LLC) 107 0 138 x 2/LLC 1 x 2/LLC 2 x 2/LLC -106 MHB542 The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Section 15.2.19 Tables 55 and 56); their polarity can be inverted via RTP0 and/or RTP1. The signals HREF and HS are available on pin XRH (see Section 15.2.20 Table 57). Fig.23 Horizontal timing diagram (50/60 Hz). 2000 Mar 15 36 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.3 Scaler SAA7114H The High Performance video Scaler (HPS) is based on the system as implemented in SAA7140, but enhanced in some aspects. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuous transfers, and handshake. The internal data flow from block to block is discontinuous dynamically, due to the scaling process itself. The flow is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks. Therefore the entire scaler acts as a pipeline buffer. Depending on the actually programmed scaling parameters the effective buffer can exceed to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced significantly. The high performance video scaler in SAA7114H has the following major blocks. * Acquisition control (horizontal and vertical timer) and task handling (the region/field/frame based processing) * Prescaler, for horizontal down-scaling by an integer factor, combined with appropriate band limiting filters, especially anti-aliasing for CIF format * Brightness, saturation, contrast control for scaled output data * Line buffer, with asynchronous read and write, to support vertical up-scaling (e.g. for videophone application, converting 240 into 288 lines, YUV 4 : 2 : 2) * Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and down-scale, or phase accurate Accumulation Mode (ACM) for large down-scaling ratios and better alias suppression * Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square (SQR) and rectangular (CCIR) pixel sampling * Output formatter for scaled YUV 4 : 2 : 2, YUV 4 : 1 : 1 and Y only (format also for raw data) * FIFO, 32-bit wide, with 64 pixel capacity in YUV formats * Output interface, 8 or 16 (only if extended by H-port) data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream. The overall H and V zooming (HV_zoom) is restricted by the input/output data rate relations. With a safety margin of 2% for running in and running out, the maximum HV_zoom is equal to: T_input_field - T_v_blanking 0.98 x ------------------------------------------------------------------------------------------------------------------------------------in_pixel x in_lines x out_cycle_per_pix x T_out_clk For example: 1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate, 1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum HV_zoom is equal to: 20 ms - 24 x 64 s 0.98 x -------------------------------------------------------- = 1.18 720 x 288 x 2 x 37 ns 2. Input from X-port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via I + H-port: 16-bit data at 27 MHz clock, 1 cycle per pixel; the maximum HV_zoom is equal to: 16.666 ms - 22 x 64 s 0.98 x ------------------------------------------------------------- = 2.34 720 x 240 x 1 x 37 ns The video scaler receives its input signal from the video decoder or from the expansion port (X-port). It gets 16-bit YUV 4 : 2 : 2 input data at a continuous rate of 13.5 MHz from the decoder. Discontinuous data stream can be accepted from the expansion port (X-port), normally 8-bit wide ITU 656 like YUV data, accompanied by a pixel qualifier on XDQ. The input data stream is sorted into two data paths, one for luminance (or raw samples), and one for time multiplexed chrominance U and V samples. An YUV 4 : 1 : 1 input format is converted to 4 : 2 : 2 for the horizontal prescaling and vertical filter scaling operation. The scaler operation is defined by two programming pages A and B, representing two different tasks, that can be applied field alternating or to define two regions in a field (e.g. with different scaling range, factors, and signal source during odd and even fields). Each programming page contains control: * For signal source selection and formats * For task handling and trigger conditions * For input and output acquisition window definition * For H-prescaler, V-scaler and H-phase scaling. 2000 Mar 15 37 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Raw VBI-data will be handled as specific input format and need an own programming page (= own task). In VBI pass through operation the processing of prescaler and vertical scaling has to be set to no-processing, but the horizontal fine scaling VPD can be activated. Upscaling (oversampling, zooming), free of frequency folding, up to factor 3.5 can be achieved, as required by some software data slicing algorithms. These raw samples are transported through the image port as valid data and can be output as Y only format. The lines are framed by SAV and EAV codes. 8.3.1 ACQUISITION CONTROL AND TASK HANDLING (SUBADDRESSES 80H, 90H, 94H TO 9FH AND C4H TO CFH) SAA7114H (XD11 to XD0, YD11 to YD0) closes the window, but the window is cut vertically, if there are less output lines than expected. The trigger events for the pixel and line counts are the horizontal and vertical reference edges as defined in subaddress 92H. The task handling is controlled by subaddress 90H (see Section 8.3.1.2). 8.3.1.1 Input field processing The acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the X-port. The acquisition window is generated via pixel and line counters at the appropriate places in the data path. From X-port only qualified pixels and lines (= lines with qualified pixel) are counted. The acquisition window parameters are: * Signal source selection regarding input video stream and formats from the decoder, or from X-port (programming bits SCSRC[1:0]91H[5:4] and FSC[2:0]91H[2:0]) Remark: The input of raw VBI-data from internal decoder should be controlled via the decoder output formatter and the LCR registers (see Section 8.2 "Decoder output formatter") * Vertical offset defined in lines of the video source, parameter YO[11:0]99H[3:0]98H[7:0] * Vertical length defined in lines of the video source, parameter YS[11:0]9BH[11:8]9AH[7:0] * Vertical length defined in number of target lines, as result of vertical scaling, parameter YD[11:0]9FH[11:8]9EH[7:0] * Horizontal offset defined in number of pixels of the video source, parameter XO[11:0]95H[3:0]94H[7:0] * Horizontal length defined in number of pixels of the video source, parameter XS[11:0]97H[3:0]96H[7:0] * Horizontal destination size, defined in target pixels after fine scaling, parameter XD[11:0]9DH[3:0]9CH[7:0]. The source start offset (XO11 to XO0, YO11 to YO0) opens the acquisition window, and the target size The trigger event for the field sequence detection from external signals (X-port) are defined in subaddress 92H. From the X-port the state of the scalers H-reference signal at the time of the V-reference edge is taken as field sequence identifier FID. For example, if the falling edge of the XRV input signal is the reference and the state of XRH input is logic 0 at that time, the detected field ID is logic 0. The bits XFDV[92H[7]] and XFDH[92H[6]] are defining the detection event and state of the flag from the X-port. For the default setting of XFDV and XFDH at `00' the state of the H-input at the falling edge of the V-input is taken. The scaler directly gets a corresponding field ID information from the SAA7114H decoder path. The FID flag is used to determine, whether the first or second field of a frame is going to be processed within the scaler and it is used as trigger condition for the task handling (see bits STRC[1:0]90H[1:0]). According to ITU 656, FID at logic 0 means first field of a frame. To ease the application, the polarities of the detection results on the X-port signals and the internal decoder ID can be changed via XFDH. As the V-sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only knows about full lines, during 1st fields from the decoder the line count of the scaler possibly shifts by one line, compared to the 2nd field. This can be compensated by switching the V-trigger event, as defined by XDV0, to the opposite V-sync edge or by using the vertical scalers phase offsets. The vertical timing of the decoder can be seen in Figs 21 and 22. As the H and V reference events inside the ITU 656 data stream (from X-port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently. 2000 Mar 15 38 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 8 Processing trigger and start DESCRIPTION Internal decoder: The processing triggers at the falling edge of the V123 pulse (see Figs 21 (50 Hz) and 22 (60 Hz)), and starts earliest with the rising edge of the decoder HREF at line number: 4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count) 2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count) External ITU 656 stream: The processing starts earliest with SAV at line number 23 (50 Hz system), respectively line 20 (60 Hz system) (according ITU 656 count) 0 0 0 XDV1 92H[5] SAA7114H XDV0 92H[4] XDH 92H[2] 1 0 0 0 0 0 8.3.1.2 Task handling Remarks: * To activate a task the start condition must be fulfilled and the acquisition window offsets must be reached. For example, in case of `start immediately', and two regions are defined for one field, the offset of the lower region must be greater than (offset + length) of upper region, if not, the actual counted H and V position at the end of the upper task is beyond the programmed offsets and the processing will `wait for next V'. * Basically the trigger conditions are checked, when a task is activated. It is important to realize, that they are not checked, while a task is inactive. So you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[2:0] = 2, YO[11:0] = 310 and task B STRC[2:0] = 3, YO[11:0] = 310 results in output field rate of 503 Hz). * After power-on or software reset (via SWRST[88H[5]]) task B gets priority over task A. The task handler controls the switching between the two programming register sets. It is controlled by subaddresses 90H and C0H. A task is enabled via the global control bits TEA[80H[4]] and TEB[80H[5]]. The handler is then triggered by events, which can be defined for each register set. In case of a programming error the task handling and the complete scaler can be reset to the initial states by the software reset bit SWRST[88H[5]] at logic 0. Especially if the programming registers, related acquisition window and scale are reprogrammed, while a task is active, a software reset must be done after programming. Contrary to the disabling/enabling of a task, which is evaluated at the end of a running task, SWRST at logic 0 sets the internal state machines directly to their idle states. The start condition for the handler is defined by bits STRC[1:0]90H[1:0] and means: start immediately, wait for next V-sync, next FID at logic 0 or next FID at logic 1. The FID is evaluated, if the vertical and horizontal offsets are reached. With RPTSK[90H[2]] at logic 1 the actual running task is repeated (under the defined trigger conditions), before handing control over to the alternate task. To support field rate reduction, the handler is also enabled to skip fields (bits FSKP[2:0]90H[5:3]) before executing the task. A TOGGLE flag is generated (used for the correct output field processing), which changes state at the beginning of a task, every time a task is activated. Examples can be seen in Section 8.3.1.3. 2000 Mar 15 39 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.3.1.3 Output field processing SAA7114H As reference for the output field processing, two signals are available for the back-end hardware. These signals are the input field ID from the scaler source and a TOOGLE flag, which shows, that an active task is used an odd (1, 3, 5...) or even (2, 4, 6...) number of times. Using a single or both tasks and reducing the field or frame rate with the task handling functionality, the TOGGLE information can be used, to reconstruct an interlaced scaled picture at a reduced frame rate. The TOGGLE flag isn't synchronized to the input field detection, as it is only dependent on the interpretation of this information by the external hardware, whether the output of the scaler is processed correctly (see Section 8.3.3). With OFIDC = 0, the scalers input field ID is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected. When OFIDC[90H[6]] = 1, the TOGGLE information is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected. Additionally the bit D7 of SAV and EAV can be defined via CONLH[90H[7]]. CONLH[90H[7]] = 0 (default) sets D7 to logic 1, a logic 1 inverts the SAV/EAV bit D7. So it's possible to mark the output of the both tasks by different SAV/EAV codes. This bit can also be seen as `task flag' on the pins IGP0 (IGP1), if TASK output is selected. 2000 Mar 15 40 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 9 Examples for field processing 2000 Mar 15 41 Philips Semiconductors PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler FIELD SEQUENCE FRAME/FIELD SUBJECT EXAMPLE 1(1) 1/1 Processed by task State of detected ITU 656 FID TOGGLE flag Bit D6 of SAV/EAV byte Required sequence conversion at the vertical scaler(8) Output(9) Notes 1. Single task every field; OFIDC = 0; subaddress 90H at 40H; TEB[80H[5]] = 0. 2. Tasks are used to scale to different output windows, priority on task B after SWRST. 3. Both tasks at 12 frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H. 4. In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted. 5. Task B at 23 frame rate constructed from neighbouring motion phases; task A at 13 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 45H. 6. Task A and B at 13 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H. 7. State of prior field. 8. It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines. 9. O = data output; NO = no output. A 0 1 0 UP UP O 1/2 A 1 0 1 LO LO O 2/1 A 0 1 0 UP UP O EXAMPLE 2(2)(3) 1/1 B 0 1 0 UP UP O 1/2 A 1 1 1 LO LO O 2/1 B 0 0 0 UP UP O 2/2 A 1 0 1 LO LO O 1/1 B 0 1 1 UP LO O EXAMPLE 3(2)(4)(5) 1/2 B 1 0 0 LO UP O 2/1 A 0 1 1 UP LO O 2/2 B 1 1 1 LO LO O 3/1 B 0 0 0 UP UP O 3/2 A 1 0 0 LO UP O 1/1 B 0 0(7) 0(7) UP UP NO EXAMPLE 4(2)(4)(6) 1/2 B 1 1 1 LO LO O 2/1 A 0 1 1 UP LO O 2/2 B 1 1(7) 1(7) LO LO NO 3/1 B 0 0 0 UP UP O 3/2 A 1 0 0 LO UP O Preliminary specification SAA7114H Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.3.2 HORIZONTAL SCALING SAA7114H The overall horizontal required scaling factor has to be split into a binary and a rational value according to the equation: output pixel H-scale ratio = ----------------------------input pixel 1 1024 H-scale ratio = --------------------------- x -----------------------------XPSC[5:0] XSCY[12:0] where, parameter of prescaler XPSC[5:0] = 1 to 63 and parameter of VPD phase interpolation XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical values). For example, 13.5 is to split in 14 x 1.14286. The binary factor is processed by the prescaler, the arbitrary non-integer ratios is achieved via the variable phase delay VPD circuitry, called horizontal fine scaling. Latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling scheme. Prescaler and fine scaler are building the horizontal scaler of the SAA7114H. Using the accumulation length function of the prescaler (XACL[5:0]A1H[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be found. * The bit XC2_1[A2H[3]], which defines the weighting of the incoming pixels during the averaging process - XC2_1 = 0 1 + 1...+ 1 +1 - XC2_1 = 1 1 + 2...+ 2 +1 The prescaler builds a prescale dependent FIR low-pass, with up to (64 + 7) filter taps. The parameter XACL[5:0] can be used to vary the low-pass characteristic for a given integer prescale of 1XPSC[5:0]. The user can therewith decide between signal bandwidth (= sharpness impression) and alias. Equation for XPSC[5:0] calculation is: Npix_in XPSC[5:0] = lower integer of ---------------------Npix_out where, the range is 1 to 63 (value 0 is not allowed!); Npix_in = number of input pixel, and Npix_out = number of desired output pixel over the complete horizontal scaler. The use of the prescaler results in a XACL[5:0] and XC2_1 dependent gain amplification. The amplification can be calculated according to the equation: DC gain = ((XACL - XC2_1) + 1) x (XC2_1 + 1) It is recommended to use sequence lengths and weights, which results in a 2N DC gain amplification, as these amplitudes can be renormalized by the XDCG[2:0] 1 controlled ------ shifter of the prescaler. N 2 The renormalization range of XDCG[2:0] is 1, 12... down to 1 128. Other amplifications have to be normalized by using the following BCS control circuitry. In these cases the prescaler has to be set to an overall gain 1, e.g. for an accumulation sequence of `1 + 1 + 1' (XACL[5:0] = 2 and XC2_1 = 0), XDCG[2:0] must be set to `010', equals 14 and the BCS has to amplify the signal to 43 (SATN[7:0] and CONT[7:0] value = lower integer of 4 x 64). 3 The use of XACL[5:0] is XPSC[5:0] dependent. XACL[5:0] must be 2 x XPSC[5:0]. XACL[5:0] can be used to find a compromise between bandwidth (= sharpness) and alias effects. 8.3.2.1 Horizontal prescaler (subaddresses A0H to A7H and D0H to D7H) The prescaling function consists of an FIR anti-alias filter stage and an integer prescaler, which is building an adaptive prescale dependent low-pass filter, to balance sharpness and aliasing effects. The FIR prefilter stage implements different low-pass characteristics to reduce alias for down-scales in the range of 1 to 12. A CIF optimized filter is build in, which reduces artefacts for CIF output formats (to be used in combination with the prescaler set to 12 scale). See Table 10. The functionality of the prescaler is defined by: * An integer prescaling ratio XPSC[5:0]A0H[5:0] (= 1 to 63), which covers the integer down-scale range 1 to 163 * An averaging sequence length XACL[5:0]A1H[5:0] (= 0 to 63); range 1 to 64 * A DC gain renormalization XDCG[2:0]A2H[2:0]; 1 down to 1128 2000 Mar 15 42 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Remark: Due to bandwidth considerations XPSC[5:0] and XACL[5:0] can be chosen different to the previous mentioned equations or Table 11, as the H-phase scaling is able to scale in the range from zooming up by factor 3 to down-scale by a factor of 10248191. Figs 26 and 27 show some resulting frequency characteristics of the prescaler. Table 11 shows the recommended prescaler programming. Other programmings, than documented in Table 11, may result in better alias suppression, but the resulting DC gain amplification needs to be compensated by the BCS control, according to the equation: 2 CONT[7:0] = SATN[7:0] = lower integer of --------------------------------DC gain x 64 XDG[2:0] SAA7114H Where: 2XDCG[2:0] DC gain DC gain = (XC2_1 + 1) x XACL[5:0] + (1 - XC2_1). For example, if XACL[5:0] = 5, XC2_1 = 1, then DC gain = 10 and the required XDCG[2:0] = 4. The horizontal source acquisition timing and the prescaling ratio is identical for both luminance path and chrominance path, but the FIR filter settings can be defined differently in the two channels. Fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling. Figs 24 and 25 show the frequency characteristics of the selectable FIR filters. Table 10 FIR prefilter functions PFUV[1:0]A2H[7:6] PFY[1:0]A2H[5:4] 00 01 10 11 LUMINANCE FILTER COEFFICIENTS bypassed 121 -1 1 1.75 4.5 1.75 1 -1 12221 CHROMINANCE COEFFICIENTS bypassed 121 3 8 10 8 3 12221 handbook, full pagewidth 6 MHB543 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 (1) PFY[1:0] = 01. (2) PFY[1:0] = 10. (3) PFY[1:0] = 11. -36 -39 -42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 f_sig/f_clock 0.5 (3) (2) (1) Fig.24 Luminance prefilter characteristic. 2000 Mar 15 43 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth 6 MHB544 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 (1) PFUV[1:0] = 01. (2) PFUV[1:0] = 10. (3) PFUV[1:0] = 11. -39 -42 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 f_sig/f_clock (2) (3) (1) Fig.25 Chrominance prefilter characteristic. handbook, full pagewidth 6 MHB545 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 f_sig/f_clock 0.5 (5) (4) (3) (2) (1) 1 XC2_1 = 0; Zero's at f = n x ------------------------ with XACL = (1), (2), (3), (4) or (5) XACL + 1 Fig.26 Examples for prescaler filter characteristics: effect of increasing XACL[5:0]. 2000 Mar 15 44 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth 6 MHB546 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 0 0.05 0.1 0.15 0.2 (2) (6) (5) (4) (3) (1) 3 dB at 0.25 6 dB at 0.33 0.25 0.3 0.35 0.4 0.45 f_sig/f_clock 0.5 (1) (2) (3) (4) (5) (6) XC2_1 = 0 and XACL[5:0] = 1. XC2_1 = 1 and XACL[5:0] = 2. XC2_1 = 0 and XACL[5:0] = 3. XC2_1 = 1 and XACL[5:0] = 4. XC2_1 = 0 and XACL[5:0] = 7. XC2_1 = 1 and XACL[5:0] = 8. Fig.27 Examples for prescaler filter characteristics: setting XC2_1 =1. 2000 Mar 15 45 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 11 XACL[5:0] usage example RECOMMENDED VALUES PRESCALE RATIO XPS [5:0] FOR LOWER BANDWIDTH REQUIREMENTS XACL[5:0] 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 1 1 1 1 1 1 1 SAA7114H FOR HIGHER BANDWIDTH REQUIREMENTS XACL[5:0] 0 1 3 4 7 7 7 8 (1) 16 XC2_1 0 1 (1 2 1) x 1 (1) 4 XDCG[2:0] 0 2 3 1 (1) 8 XC2_1 0 0 (1 1) x 0 1 (1) 2 XDCG[2:0] 0 1 2 FIR PREFILTER PFY[1:0]/ PFUV[1:0] 0 to 2 0 to 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 1 2 3 4 5 6 7 8 9 10 13 15 16 19 31 32 35 0 2 4 8 8 8 8 15 15 16 16 31 32 32 32 63 63 1 (1 2 2 2 1) x 1 (1 2 2 2 2 2 2 2 1) x 116(1) 1 (1 2 2 2 2 2 2 2 1) x 1 (1 2 2 2 2 2 2 2 1) x 1 (1 2 2 2 2 2 2 2 1) x 116(1) 0 0 1 1 0 1 1 1 1 1 1 (1) 16 1 (1) 16 (1 1 1 1) x 4 4 4 4 4 1 1 (1) 4 1 (1 2 2 2 1) x 18(1) 0 (1 1 1 1 1 1 1 1) x 0 (1 1 1 1 1 1 1 1) x 0 (1 1 1 1 1 1 1 1) x 18(1) 1 1 1 1 1 1 1 1 1 1 1 (1) 8 1 (1) 8 3 3 3 3 4 1 (1) 16 (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) x (1 2 2 2 2 2 2 2 1) x 8 8 4 5 1 (1) 32 4 4 1 (1) 16 (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) x 116(1) 10 (1 2 2 2 2 2 2 2 1) x 116(1) (1 2 2 2 2 2 2 2 1) x 16 16 16 32 32 32 63 (1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1) x 13 15 16 19 31 32 35 5 5 6 6 6 7 7 5 5 5 6 6 6 7 Note 1. Resulting FIR function. 2000 Mar 15 46 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.3.2.2 Horizontal fine scaling (variable phase delay filter; subaddresses A8H to AFH and D8H to DFH) 8.3.3.1 SAA7114H Line FIFO buffer (subaddresses 91H, B4H and C1H, E4H) The horizontal fine scaling (VPD) should operate at scaling ratios between 12 and 2 (0.8 and 1.6), but can also be used for direct scale in the range from 17.999 to (theoretical) zoom 3.5 (restriction due to the internal data path architecture), without prescaler. In combination with the prescaler a compromise between sharpness impression and alias can be found, which is signal source and application dependent. For the luminance channel a filter structure with 10 taps is implemented, for the chrominance a filter with 4 taps. Luminance and chrominance scale increments (XSCY[12:0]A9H[4:0]A8H[7:0] and XSCC[12:0]ADH[4:0]ACH[7:0]) are defined independently, but must be set in a 2 : 1 relation in the actual data path implementation. The phase offsets XPHY[7:0]AAH[7:0] and XPHC[7:0]AEH[7:0] can be used to shift the sample phases slightly. XPHY[7:0] and XPHC[7:0] covers the phase offset range 7.999T to 132T. The phase offsets should also be programmed in a 2 : 1 ratio. The underlying phase controlling DTO has a 13-bit resolution. According to the equations Npix_in 1 XSCY[12:0] = 1024 x ------------------- x ---------------------- and XPSC Npix_out XSCY[12:0] XSCC[12:0] = ------------------------------ the VPD covers the scale 2 range from 0.125 to zoom 3.5. VPD acts equivalent to a polyphase filter with 64 possible phases. In combination with the prescaler, it is possible to get very accurate samples from a highly anti-aliased integer down-scaled input picture. 8.3.3 VERTICAL SCALING The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous write and read access. The line buffer can be used for various functions, but not all functions may be available simultaneously. The line buffer can buffer a complete unscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up. For zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation. For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling scheme (MPEG, video phone, video YUV-9) to CCIR like sampling scheme 4 : 2 : 2, the chrominance line buffer is read twice of four times, before being refilled again by the source. By means of the input acquisition window definition it has to be preserved, that the processing starts with a line containing luminance and chrominance information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits FSC[2:1]91H[2:1] are defining the distance between the Y/C lines. In case of 4 : 2 : 2 and 4 : 1 : 1 FSC2 to FSC1 have to be set to `00'. The line buffer can also be used for mirroring, i.e. for flipping the image left to right, for the vanity picture in video phone application (bit YMIR[B4H[4]]). In mirror mode only one active prescaled line can be held in the FIFO at a time. The line buffer can be utilized as excessive pipeline buffer for discontinuous and variable rate transfer conditions at expansion port or image port. The vertical scaler of the SAA7114H consists of a line FIFO buffer for line repetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size 164. The vertical scaler is located between the BCS and horizontal fine scaler, so that the BCS can be used to compensate the DC gain amplification of the ACM mode (see Section 8.3.3.2) as the internal RAMs are only 8-bit wide. 2000 Mar 15 47 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.3.3.2 Vertical scaler (subaddresses B0H to BFH and E0H to EFH) SAA7114H and field rate conversion are supported (i.e. de-interlacing, re-interlacing). Figs 28 and 29 and Tables 12 and 13 are describing the use of the offsets. Remark: The vertical start phase, as well as scaling ratio are defined independently for luminance and chrominance channel, but must be set to the same values in the actual implementation for accurate 4 : 2 : 2 output processing. The vertical processing communicates on it's input side with the line FIFO buffer. The scale related equations are: * Scaling increment calculation for ACM and LPI mode, down-scale and zoom: Nline_in YSCY(C)[15:0] = lower integer of 1024 x ------------------------ Nline_out * BCS value to compensate DC gain in ACM mode (contrast and saturation have to be set): CONT[7:0]A5H[7:0] respectively SATN[7:0]A6H[7:0] Nline_out = lower integer of ------------------------ x 64 , or Nline_in 1024 = lower integer of ------------------------------ x 64 YSCY[15:0] Vertical scaling of any ratio from 64 (theoretical zoom) to 1 (icon) can be applied. 63 The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes. Called linear interpolation (LPI) and accumulation (ACM) mode, controlled by YMODE[B4H[0]]. * LPI mode: In Linear Phase Interpolation (LPI) mode (YMODE = 0) two neighbouring lines of the source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. This linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. It interpolates between two consecutive input lines only. LPI mode should be applied for scaling ratios around 1 (down to 12), it must be applied for vertical zooming. * ACM mode: The vertical Accumulation (ACM) mode (YMODE = 1) represents a vertical averaging window over multiple lines, sliding over the field. This mode also generates phase correct output lines. The averaging window length corresponds to the scaling ration, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. ACM can be applied for down-scales only from ratio 1 down to 164. ACM results in a scale dependent DC gain amplification, which has to be precorrected by the BCS control of the scaler part. The phase and scale controlling DTO calculates in 16-bit resolution, controlled by parameters YSCY[15:0]B1H[7:0]B0H[7:0] and YSCC[15:0]B3H[7:0]B2H[7:0], continuously over the entire filed. A start offset can be applied to the phase processing by means of the parameters YPY3[7:0] to YPY0[7:0] in BFH[7:0] to BCH[7:0] and YPC3[7:0] to YPC0[7:0] in BBH[7:0] to B8H[7:0]. The start phase covers the range of 25532 to 132 lines offset. By programming appropriate, opposite, vertical start phase values (subaddresses B8H to BFH and E8H to EFH) depending on odd/even field ID of the source video stream and A/B-page cycle, frame ID conversion 8.3.3.3 Use of the vertical phase offsets As shown in Section 8.3.1.3, the scaler processing may run randomly over the interlaced input sequence. Additionally the interpretation and timing between ITU 656 field ID and real-time detection by means of the state of H-sync at falling edge of V-sync may result in different field ID interpretation. Also a vertically scaled interlaced output gets a larger vertical sampling phase error, if the interlaced input fields are processed, without regarding the actual scale at the starting point of operation (see Fig.28). Four events are to be considered, they are illustrated in Fig.29. 2000 Mar 15 48 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth unscaled input field 2 scaled output, no phase offset field 1 field 2 scaled output, with phase offset field 1 field 2 field 1 correct scale dependent position scale dependent start offset mismatched vertical line distances MHB547 Fig.28 Basic problem of interlaced vertical scaling (example: down-scale 35). handbook, full pagewidth field 1 upper field 2 lower A field 1 case UP-UP field 2 case LO-LO B field 1 case UP-LO field 2 case LO-UP C D MHB548 1024 Offset = ------------ = 32 = 1 line shift 32 1 A = -- input line shift = 16 2 1 1 YSCY[15:0] B = -- input line shift + -- scale increment = ------------------------------ + 16 2 2 64 1 YSCY[15:0] C = -- scale increment = -----------------------------2 64 D = no offset = 0 Fig.29 Derivation of the phase related equations (example: interlace vertical scaling down to 35, with field conversion). 2000 Mar 15 49 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler In Tables 12 and 13 PHO is a usable common phase offset. Please notice that the equations of Fig.29 are producing an interpolated output also for the unscaled case, as the geometrical reference position for all conversions is the position of the first line of the lower field (see Table 12). If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the 12 line phase shift (PHO + 16) can be skipped. This case is listed in Table 13. The SAA7114H supports 4 phase offset registers per task and component (luminance and chrominance). The value of 20H represents a phase shift of one line. SAA7114H The registers are assigned to the following events; e.g. subaddresses B8H to BBH: * B8H: 00 = input field ID 0, task status bit 0 (toggle status, see Section 8.3.1.3) * B9H: 01 = input field ID 0, task status bit 1 * BAH: 10 = input field ID 1, task status bit 0 * BBH: 11 = input field ID 1, task status bit 1. Dependent on the input signal (interlaced or non-interlaced) and the task processing (50 Hz or field reduced processing with one or two tasks, see examples in Section 8.3.1.3), also other combinations may be possible, but the basic equations are the same. Table 12 Examples for vertical phase offset usage: global equations INPUT FIELD UNDER PROCESSING Upper input lines Upper input lines Lower input lines Lower input lines OUTPUT FIELD USED ABBREVIATION INTERPRETED AS upper output lines lower output lines upper output lines Lower output lines UP-UP UP-LO LO-UP LO-LO EQUATION FOR PHASE OFFSET CALCULATION (DECIMAL VALUES) PHO + 16 YSCY[15:0] PHO + ------------------------------ + 16 64 PHO YSCY[15:0] PHO + -----------------------------64 2000 Mar 15 50 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 13 Vertical phase offset usage; assignment of the phase offsets DETECTED INPUT FIELD ID 0 = upper lines TASK STATUS BIT 0 VERTICAL PHASE OFFSET YPY(C)0[7:0] CASE SAA7114H EQUATION TO BE USED case 1(1) UP-UP (PHO) case 2(2) UP-UP case 3(3) UP-LO 0 = upper lines 1 YPY(C)1[7:0] case 1 case 2 case 3 UP-UP (PHO) UP-LO UP-UP YSCY[15:0] LO-LO PHO + ------------------------------ - 16 64 LO-UP LO-LO YSCY[15:0] LO-LO PHO + ------------------------------ - 16 64 LO-LO LO-UP 1 = lower lines 0 YPY(C)2[7:0] case 1 case 2 case 3 1 = lower lines 1 YPY(C)3[7:0] case 1 case 2 case 3 Notes 1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper output lines. 2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output lines. 3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output lines. 2000 Mar 15 51 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.4 VBI-data decoder and capture (subaddresses 40H to 7FH) SAA7114H The SAA7114H contains a versatile VBI-data decoder. The implementation and programming model accords to the VBI-data slicer built in the multimedia video data acquisition circuit SAA5284. The circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them to bytes. The result is buffered into a dedicated VBI-data FIFO with a capacity of 2 x 56 bytes (2 x 14 Dwords). The clock frequency, signals source, field frequency, accepted error count must be defined in subaddress 40H. The supported VBI-data standards are shown in Table 14. For lines 2 to 24 of a field, per VBI line, 1 of 16 standards can be selected (LCR24_[7:0] to LCR2_[7:0] in 57H[7:0] to 41H[7:0]: 23 x 2 x 4 bit programming bits). Table 14 Data types supported by the data slicer block DT[3:0] 62H[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 US NABTS MOJI (Japanese) no sliced data transmitted (video data selected) 5.7272 5.7272 5 STANDARD TYPE teletext EuroWST, CCST European closed caption VPS wide screen signalling bits US teletext (WST) US closed caption (line 21) (video data selected) (raw data selected) teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) The definition for line 24 is valid for the rest of the corresponding field, normally no text data (= video data) should be selected there (LCR24_[7:0] = FFH) to stop the activity of the VBI-data slicer during active video. To adjust the slicers processing to the input signal source, there are offsets in horizontal and vertical direction available: parameters HOFF[10:0]5BH[2:0]59H[7:0], VOFF[8:0]5BH[4]5AH[7:0] and FOFF[5BH[7]]). Contrary to the scalers counting, the slicers offsets are defining the position of the H and V trigger events related to the processed video field. The trigger events are the falling edge of HREF and the falling edge of V123 from the decoder processing part. The relation of these programming values to the input signal and the recommended values can be seen in Tables 4 to 7. DATA RATE (Mbits/s) 6.9375 0.500 5 5 5.7272 0.503 5 5 6.9375 1.8125 1.7898 FRAMING CODE 27H 001 9951H 1E3C1FH 27H 001 none none programmable programmable programmable FC WINDOW WST625 CC625 VPS WSS WST525 CC525 disable disable general text VITC625 VITC625 NABTS open disable HAM CHECK always always optional reserved programmable programmable none optional programmable (A7H) Japtext Japanese format switch (L20/22) 5 2000 Mar 15 52 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.5 Image port output formatter (subaddresses 84H to 87H) SAA7114H The bits VITX1 and VITX0 (subaddress 86H) are used to control the arbitration. As further operation the serialization of the internal 32-bit Dwords to 8-bit or optional 16-bit output, as well as the insertion of the extended ITU 656 codes (SAV/EAV for video data, ANC or SAV/EAV codes for sliced text data) are done here. For handshake with the VGA controller, or other memory or bus interface circuitry, programmable FIFO flags are provided (see Section 8.5.2). 8.5.1 SCALER OUTPUT FORMATTER (SUBADDRESSES 93H AND C3H) The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I-port and a decoding and multiplexing unit, which generates the 8 or 16-bit wide output data stream and the accompanied reference and supporting information. The clock for the output interface can be derived from an internal clock, decoder, expansion port, or an externally provided clock which is appropriate for e.g. VGA and frame buffer. The clock can be up to 33 MHz. The scaler provides the following video related timing reference events (signals), which are available on pins as defined by subaddresses 84H and 85H: * Output field ID * Start and end of vertical active video range, * Start and end of active video line * Data qualifier or gated clock * Actually activated programming page (if CONLH is used) * Threshold controlled FIFO filling flags (empty, full, filled) * Sliced data marker. The disconnected data stream at the scaler output is accompanied by a data valid flag (or data qualifier), or is transported via a gated clock. Clock cycles with invalid data on the I-port data bus (including the HPD pins in 16-bit output mode) are marked with code 00H. The output interface also arbitrates the transfer between scaled video data and sliced text data over the I-port output. Table 15 Byte stream for different output formats OUTPUT FORMAT YUV 4 : 2 : 2 YUV 4 : 1 : 1 Y only CB0 CB0 Y0 Y0 Y0 Y1 CR0 CR0 Y2 The output formatter organizes the packing into the output FIFO. The following formats are available: YUV 4 : 2 : 2, YUV 4 : 1 : 1, YUV 4 : 2 : 0, YUV 4 : 1 : 0, Y only (e.g. for raw samples). The formatting is controlled by FSI[2:0]93H[2:0], FOI[1:0]93H[4:3] and FYSK[93H[5]]. The data formats are defined on Dwords, or multiples, and are similar to the video formats as recommended for PCI multimedia applications (compare SAA7146A), but planar formats are not supported. FSI[2:0] defines the horizontal packing of the data, FOI[1:0] defines, how many Y only lines are expected, before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only lines will be skipped, and output will always start with a Y/C line. Additionally the output formatter limits the amplitude range of the video data (controlled by ILLV[85H[5]]); see Table 17. BYTE SEQUENCE FOR 8-BIT OUTPUT MODES Y1 Y1 Y3 CB2 CB4 Y4 Y2 Y2 Y5 CR2 CR4 Y6 Y3 Y3 Y7 CB4 Y4 Y8 Y4 Y5 Y9 CR4 Y6 Y10 Y5 Y7 Y11 CB6 CB8 Y12 Y6 Y8 Y13 Table 16 Explanation to Table 15 NAME CBn Yn CRn EXPLANATION U (B - Y) colour difference component, pixel number n = 0, 2, 4 to 718 Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 V (R - Y) colour difference component, pixel number n = 0, 2, 4 to 718 2000 Mar 15 53 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 17 Limiting range on I-port LIMIT STEP ILLV[85H[5]] 0 1 8.5.2 VALID RANGE DECIMAL VALUE 1 to 254 8 to 247 VIDEO FIFO (SUBADDRESS 86H) HEXADECIMAL VALUE 01 to FE 08 to F7 SAA7114H SUPPRESSED CODES (HEXADECIMAL VALUE) LOWER RANGE 00 00 to 07 UPPER RANGE FF F8 to FF The video FIFO at the scaler output contains 32 Dwords. That corresponds to 64 pixels in 16-bit YUV 4 : 2 : 2 format. But as the entire scaler can act as pipeline buffer, the actually available buffer capacity for the image port is much higher, and can exceed beyond a video line. The image port, and the video FIFO, can operate with the video source clock (synchronous mode) or with externally provided clock (asynchronous, and burst mode), as appropriate for the VGA controller or attached frame buffer. The video FIFO provides 4 internal flags, reporting to which extent the FIFO is actually filled. These are: * The FIFO Almost Empty (FAE) flag * The FIFO Combined Flag (FCF) or FIFO filled, which is set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark * The FIFO Almost Full (FAF) flag * The FIFO Overflow (FOVL) flag. The trigger levels for FAE and FAF are programmable by FFL[1:0]86H[3:2] (16, 24, 28, full) and FEL[1:0]86H[1:0] (16, 8, 4, empty). The state of this flag can be seen on the pins IGP0 or IGP1. The pin mapping is defined by subaddresses 84H and 85H (see Section 9.5). 8.5.3 TEXT FIFO The decoded VBI-data is collected in the dedicated VBI-data FIFO. After capture of a line is completed, the FIFO can be streamed through the image port, preceded by a header, telling line number and standard. The VBI-data period can be signalled via the sliced data flag on pin IGP0 or IGP1. The decoded VBI-data is lead by the ITU ancillary data header (DID[5:0]5DH[5:0] at value <3EH) or by SAV/EAV codes selectable by DID[5:0] at value 3EH or 3FH. IGP0 or IGP1 is set, if the first byte of the ANC header is valid on the I-port bus. It is reset, if an SAV occurs. So it may frame multiple lines of text data output, in case video processing starts with a distance of several video lines to the region of text data. Valid sliced data from the text FIFO are available on the I-port as long as the IGP0 or IGP1 flag is set and the data qualifier is active on pin IDQ. The decoded VBI-data are presented in two different data formats, controlled by bit RECODE. * RECODE = 1: values 00H and FFH will be recoded to even parity values 03H and FCH * RECODE = 0: values 00H and FFH may occur in the data stream as detected. 8.5.4 VIDEO AND TEXT ARBITRATION (SUBADDRESS 86H) In the text FIFO the data of the terminal VBI-data slicer are collected before the transmission over the I-port is requested (normally before the video window starts). It is partitioned into two FIFO sections. A complete line is filled into the FIFO, before a data transfer is requested. So normally, one line text data is ready for transfer, while the next text line is collected. So sliced text data are delivered as a block of qualified data, without any qualification gaps in the byte stream of the I-port. Sliced text data and scaled video data are transferred over the same bus, the I-port. The mixed transfer is controlled by an arbitration circuitry. If the video data are transferred without any interrupt and the video FIFO does not need to buffer any output pixel, the text data are inserted after an end of a scaled video line, normally during the blanking interval of the video. 2000 Mar 15 54 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.5.5 GENERATION SAA7114H DATA STREAM CODING AND REFERENCE SIGNAL (SUBADDRESSES 84H, 85H AND 93H) If ITU 656 like codes are not wanted, these codes can be suppressed in the output stream. As further option, it is possible to provide the scaler with a gating external signal on pin ITRDY. So it is possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length. The sketched reference signals and events can be mapped to the I-port output pins IDQ, IGPH, IGPV, IGP0 and IGP1. For flexible use the polarities of all the outputs can be modified. The default polarity for the qualifier and reference signals is logic 1 (= active). Table 18 shows the relevant and supported SAV and EAV coding. As H and V reference signals are logic 1, active gate signals are generated, which are framing the transfer of the valid output data. Alternative to the gates, H and V trigger pulses are generated on the rising edges of the gates. Due to the dynamic FIFO behaviour of the complete scaler path, the output signal timing has no fixed timing relation to the real-time input video stream. So fixed propagation delays, in therms of clock cycles, related to the analog input can not be defined. The data stream is accompanied by a data qualifier. Additionally invalid data cycles are marked with code 00H. Table 18 SAV/EAV codes on I-port SAV/EAV CODES ON I-PORT(1) (HEX) EVENT DESCRIPTION MSB(2) OF SAV/EAV BYTE = 0 MSB(2) OF SAV/EAV BYTE = 1 FIELD ID = 0 Next pixel is FIRST pixel of any active line Previous pixel was LAST pixel of any active line, but not the last Next pixel is FIRST pixel of any V-blanking line Previous pixel was LAST pixel of the last active line or of any V-blanking line No valid data, don't capture and don't increment pointer Notes 1. The leading byte sequence is: FFH-00H-00H. 2. The MSB of the SAV/EAV code byte is controlled by: a) Scaler output data: task A MSB = CONLH (90H[7]); task B MSB = CONLH (C0H[7]). b) VBI-data slicer output data: DID[5:0]5DH[5:0] = 3EH MSB = 1; DID[5:0]5DH[5:0] = 3FH MSB = 0. 0E 13 FIELD ID = 1 49 54 FIELD ID = 0 80 9D FIELD ID = 1 C7 DA HREF = active; VREF = active HREF = inactive; VREF = active HREF = active; VREF = inactive HREF = inactive; VREF = inactive IDQ pin inactive COMMENT 25 38 62 7F AB B6 EC F1 00 2000 Mar 15 55 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Mar 15 ... Philips Semiconductors PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler invalid data or end of raw VBI line timing reference code FF 00 00 internal header IDI1 sliced data IDI2 D1_3 D1_4 D2_1 and filling data timing reference code BC FF 00 00 EAV invalid data 00 00 ... FF 00 00 00 00 EAV SAV SDID DC ... DDC_3 DDC_4 CS ... MHB549 D1_1 D1_2 ANC header 00 FF FF internal header DID SDID DC IDI1 sliced data IDI2 D1_3 D1_4 ... DDC_3 DDC_4 CS BC ANC data output is only filled up to the Dword boundary 00 00 ... ANC header active for DID (subaddress 5DH) <3EH Fig.30 Sliced data formats on the I-port in 8-bit mode. Table 19 Explanation to Fig.30 NAME SAV SDID 56 DC start of active data; see Table 20 sliced data identification: NEP(1), EP(2), SDID5 to SDID0, freely programmable via I2C-bus subaddress 5EH, D5 to D0, e. g. to be used as source identifier Dword count: NEP(1), EP(2), DC5 to DC0. DC describes the number of succeeding 32-bit words: * For SAV/EAV mode DC is fixed to 11 Dwords (byte value 4BH) * For ANC mode it is: DC = 14(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes according to the chosen text standard. Note that the number of valid bytes inside the stream can be seen in the BC byte. IDI1 IDI2 Dn_m DDC_4 CS BC EAV Notes 1. Inverted EP (bit 7); for EP see note 2. 2. Even parity (bit 6) of bits 5 to 0. 3. Odd parity (bit 7) of bits 6 to 0. internal data identification 1: OP(3), FID (field 1 = 0, field 2 = 1), LineNumber8 to LineNumber3 = Dword 1 byte 1; see Table 20 internal data identification 2: OP(3), LineNumber2 to LineNumber0, DataType3 to DataType0 = Dword 1 byte 2; see Table 20 Dword number n, byte number m last Dword byte 4, note: for SAV/EAV framing DC is fixed to 0BH, missing data bytes are filled up; the fill value is A0H the check sum byte, the checksum is accumulated from the SAV (respectively DID) byte to the DDC_4 byte number of valid sliced bytes counted from the IDI1 byte end of active data; see Table 20 EXPLANATION Preliminary specification SAA7114H Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 20 Bytes stream of the data slicer NICK NAME DID, SAV, EAV COMMENT subaddress 5DH = 00H subaddress 5DH; D5 = 1 subaddress 5DH D5 = 3EH; note 5 subaddress 5DH D5 = 3FH; note 5 SDID DC(8) IDI1 IDI2 CS BC Notes 1. NEP = inverted EP (see note 2). 2. EP = Even Parity of bits 5 to 0. 3. FID = 0: field 1; FID = 1: field 2. check sum byte valid byte count programmable via subaddress 5EH D7 NEP(1) NEP 1 0 NEP NEP OP(9) OP CS6 OP D6 EP(2) EP FID(3) FID(3) EP EP(2) FID(3) LN2(10) CS6 0 D5 0 0 V(6) V(6) D4 1 D3 0 D2 FID(3) SAA7114H D1 I1(4) D0 I0(4) D4[5DH] D3[5DH] D2[5DH] D1[5DH] D0[5DH] H(7) H(7) P3 P3 P2 P2 P1 P1 P0 P0 D5[5EH] D4[5EH] D3[5EH] D2[5EH] D1[5EH] D0[5EH] DC5 LN8(10) LN1(10) CS5 CNT5 DC4 LN7(10) LN0(10) CS4 CNT4 DC3 LN6(10) DT3(11) CS3 CNT3 DC2 LN5(10) DT2(11) CS2 CNT2 DC1 LN4(10) DT1(11) CS1 CNT1 DC0 LN3(10) DT0(11) CS0 CNT0 4. I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1: line 24 to end of field. 5. Subaddress 5DH at 3EH and 3FH are used for ITU 656 like SAV/EAV header generation; recommended value. 6. V = 0: active video; V = 1: blanking. 7. H = 0: start of line; H = 1: end of line. 8. DC = Data Count in Dwords according to the data type. 9. OP = Odd Parity of bits 6 to 0. 10. LN = Line Number. 11. DT = Data Type according to table. 2000 Mar 15 57 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.6 Audio clock generation (subaddresses 30H to 3FH) SAA7114H * Audio master Clocks Nominal Increment, ACNI[21:0]36H[5:0]35H[7:0]34H[7:0] according to the audio frequency 23 equation: ACNI21:0] = round -------------------------------------------- x 2 crystal frequency See Table 21 for examples. Remark: For standard applications the synthesized audio clock AMCLK can be used directly as master clock and as input clock for port AMXCLK (short cut) to generate ASCLK and ALRCLK. For high-end applications it is recommended to use an external analog PLL circuit to enhance the performance of the generated audio clock. SAA7114H incorporates generation of a field locked audio clock, as an auxiliary function for video capture. An audio sample clock, that is locked to the field frequency, makes sure that there is always the same predefined number of audio samples associated with a field, or a set of fields. That ensures synchronous playback of audio and video after digital recording (e.g. capture to hard disk), MPEG or other compression, or non-linear editing. 8.6.1 MASTER AUDIO CLOCK The audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. The master audio clock is defined by the parameters: * Audio master Clocks Per Field, ACPF[17:0]32H[1:0]31H[7:0]30H[7:0] according to the audio frequency equation: ACPF[17:0] = round ----------------------------------------- field frequency- Table 21 Programming examples for audio master clock generation ACPF XTALO (MHz) FIELD (Hz) DECIMAL AMCLK = 256 x 48 kHz (12.288 MHz) 32.11 24.576 50 59.94 50 59.94 245760 205005 - - 225792 188348 225792 188348 3C000 320CD - - 37200 2DFBC 37200 2DFBC 3210190 3210190 - - 2949362 2949362 3853517 3853 517 30FBCE 30FBCE - - 2D00F2 2D00F2 3ACCCD 3ACCCD HEX DECIMAL HEX ACNI AMCLK = 256 x 44.1 kHz (11.2896 MHz) 32.11 24.576 50 59.94 50 59.94 AMCLK = 256 x 32 kHz (8.192 MHz) 32.11 24.576 50 59.94 50 59.94 163840 136670 163840 136670 28000 215DE 28000 215DE 2140127 2140127 2796203 2796203 20A7DF 20A7DF 2AAAAB 2AAAAB 2000 Mar 15 58 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 8.6.2 SIGNALS ASCLK AND ALRCLK SAA7114H Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for channel-select. The frequencies of these signals are defined by the parameters: * SDIV[5:0]38H[5:0] according to the equation: f AMXCLK f AMXCLK f ASCLK = ------------------------------------- SDIV[5:0] = ------------------- - 1 2f ASCLK ( SDIV + 1 ) x 2 * LRDIV[5:0]39H[5:0] according to the equation: f ASCLK f ASCLK f ALRCLK = -------------------------- LRDIV[5:0] = ---------------------LRDIV x 2 2f ALRCLK See Table 22 for examples. Table 22 Programming examples for ASCLK/ALRCLK clock generation AMXCLK (MHz) 12.288 11.2896 8.192 ASCLK (kHz) 1536 768 1411.2 2822.4 1024 2048 SDIV DECIMAL 3 7 3 1 3 1 HEX 03 07 03 01 03 01 ALRCLK (kHz) 48 44.1 32 LRDIV DECIMAL 16 8 16 32 16 32 HEX 10 08 10 10 10 10 8.6.3 OTHER CONTROL SIGNALS LRPH[3AH[1]]; ALRCLK Phase 0: invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK 1: don't invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK SCPH[3AH[0]]; ASCLK Phase: 0: invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK 1: don't invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK Further control signals are available to define reference clock edges and vertical references: APLL[3AH[3]]; Audio PLL mode: 0: PLL closed 1: PLL open AMVR[3AH[2]]; Audio Master clock Vertical Reference: 0: internal V 1: external V 2000 Mar 15 59 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 9 INPUT/OUTPUT INTERFACES AND PORTS 9.1 Analog terminals SAA7114H The SAA7114H has 5 different I/O interfaces: * Analog video input interface, for analog CVBS and/or Y and C input signals * Audio clock port * Digital real-time signal port (RT port) * Digital video expansion port (X-port), for unscaled digital video input and output * Digital image port (I-port) for scaled video data output and programming * Digital host port (H-port) for extension of the image port or expansion port from 8 to 16-bit. The SAA7114H has 6 analog inputs AI21 to AI24, AI11 and AI12 for composite video CVBS or S-video Y/C signal pairs. Additionally, there are two differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 6 inputs. There are no peripheral components required other than these decoupling capacitors and 18 /56 termination resistors, one set per connected input signal (see also application example in Fig.40). Two anti-alias filters are integrated, and self adjusting via the clock frequency. Clamp and gain control for the two ADC's are also integrated. An analog video output pin AOUT is provided for testing purposes. Table 23 Analog pin description SYMBOL AI24 to AI21 AI12 and AI11 AOUT AI1D and AI2D PIN 10, 12, 14 and 16 18 and 20 22 19 and 13 O I I/O I DESCRIPTION analog video signal inputs, e.g. 2 CVBS signals and two Y/C pairs can be connected simultaneously analog video output, for test purposes analog reference pins for differential ADC operation BIT MODE3 to MODE0 AOSL1 and AOSL0 - 9.2 Audio clock signals The SAA7114H also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow PLL. This ensures that the multimedia capture and compression processes always gather the same predefined number of samples per video frame. Table 24 Audio clock pin description SYMBOL PIN I/O AMCLK AMXCLK 37 41 O I DESCRIPTION audio master clock output An audio master clock AMCLK and two divided clocks ASCLK and ALRCLK are generated; * ASCLK: can be used as audio serial clock * ALRCLK: audio left/right channel clock. The ratios are programmable, see also Section 8.6. BIT ACPF[17:0]32H[1:0]31H[7:0]30H[7:0] and ACNI[21:0]36H[5:0]35H[7:0]34H[7:0] - external audio master clock input for the clock division circuit, can be directly connected to output AMCLK for standard applications serial audio clock output, can be synchronized to rising or falling edge of AMXCLK audio channel (left/right) clock output, can be synchronized to rising or falling edge of ASCLK ASCLK ALRCLK 39 40 O O SDIV[5:0]38H[5:0] and SCPH[3AH[0]] LRDIV[5:0]39H[5:0] and LRPH[3AH[1]] 2000 Mar 15 60 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 9.3 Clock and real-time synchronization signals SAA7114H For the generation of the line-locked video (pixel) clock LLC, and of the frame locked audio serial bit clock, a crystal accurate frequency reference is required. An oscillator is built in, for fundamental or third harmonic crystals. The supported crystal frequencies are 32.11 or 24.576 MHz (defined during reset by strapping pin ALRCLK). Alternatively pin XTALI can be driven from an external single ended oscillator. The crystal oscillation can be propagated as clock to other ICs in the system via pin XOUT. Table 25 Clock and real-time synchronization signals SYMBOL PIN I/O Crystal oscillator XTALI XTALO XOUT 7 6 4 I O O The Line-Locked Clock (LLC) is the double pixel clock of nominal 27 MHz. It is locked to the selected video input, generating baseband video pixels according to "ITU recommendation 601". In order to support interfacing circuitries, a direct pixel clock LLC2 is also provided. The pins for line and field timing reference signals are RTCO, RTS1 and RTS0. Various real-time status information can be selected for the RTS pins. The signals are always available (output) and reflect the synchronization operation of the decoder part in the SAA7114H. The function of the RTS1 and RTS0 pins can be defined by bits RTSE1[3:0]12H[7:4] and RTSE0[3:0]12H[3:0]. DESCRIPTION - - BIT input for crystal oscillator, or reference clock output of crystal oscillator reference (crystal) clock output drive (optional) XTOUTE[14H[3]] - - - Real-time signals (RT port) LLC LLC2 RTCO 28 29 36 O O O line-locked clock, nominal 27 MHz, double pixel clock locked to the selected video input signal line-locked pixel clock, nominal 13.5 MHz real-time control output, transfers real-time status information supporting RTC level 3.1 (see external document "RTC Functional Description", available on request) real-time status information line 0, can be programmed to carry various real-time informations (see Table 55) real-time status information line 1, can be programmed to carry various real-time informations (see Table 56) RTS0 RTS1 34 35 O O RTSE0[3:0]12H[3:0] RTSE1[3:0]12H[7:4] 2000 Mar 15 61 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 9.4 Video expansion port (X-port) SAA7114H As output, these are direct copies of the decoder signals. The data transfers through the expansion port represent a single D1 port, with half duplex mode. The SAV and EAV codes may be inserted optionally for data input (controlled by bit XCODE[92H[3]]). The input/output direction is switched for complete fields, only. The expansion port is intended for transporting video streams image data from other digital video circuits like MPEG encoder/decoder and video phone codec, to the image port (I-port). The expansion port consists of two groups of signals/pins: * 8-bit data, I/O, regularly components video YUV 4 : 2 : 2, i.e. CB-Y-CR-Y, byte serial, exceptionally raw video samples (e.g. ADC test). In input mode the data bus can be extended to 16-bit by the pins HPD7 to HPD0. * Clock, synchronization and auxiliary signals, accompanying the data stream, I/O. Table 26 Signals dedicated to the expansion port SYMBOL XPD7 to XPD0 PIN I/O DESCRIPTION BIT OFTS[2:0]13H[2:0]; 91H[7:0] and C1H[7:0] 81, 82, I/O X-port data: in output mode controlled by decoder 84 to 87, section, data format see Table 27; in input mode 89 and 90 YUV 4 : 2 : 2 serial input data or luminance part of a 16-bit YUV 4 : 2 : 2 input 94 I/O clock at expansion port: if output, then copy of LLC; as input normally a double pixel clock of up to 32 MHz or a gated clock (clock gated with a qualifier) XCLK XCKS[92H[0]] XDQ 95 I/O data valid flag of the expansion port input (qualifier): - if output, then decoder (HREF and VGATE) gate (see Fig.23) O data request flag = ready to receive, to work with XRQT[83H[2]] optional buffer in external device, to prevent internal buffer overflow; second function: input related task flag A/B XRDY 96 XRH 92 I/O horizontal reference signal for the X-port: as output: XRHS[13H[6]], XFDH[92H[6]] and HREF or HS from the decoder (see Fig.23); as XDH[92H[2]] input: a reference edge for horizontal input timing and a polarity for input field ID detection can be defined I/O vertical reference signal for the X-port: as output: V123 or field ID from the decoder, see Figs 21 and 22; as input: a reference edge for vertical input timing and for input field ID detection can be defined I port control: switches X-port input 3-state XRVS[1:0]13H[5:4], XFDV[92H[7]] and XDV[1:0]92H[5:4] XRV 91 XTRI 80 XPE[1:0]83H[1:0] 2000 Mar 15 62 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 9.4.1 X-PORT CONFIGURED AS OUTPUT SAA7114H If data output is enabled at the expansion port, then the data stream from the decoder is presented. The data format of the 8-bit data bus is dependent on the chosen data type, selectable by the line control registers LCR2 to LCR24; see Table 3. In contrast to the image port, the sliced data format is not available on the expansion port. Instead, raw CVBS samples are always transferred if any sliced data type is selected. Following are some details of data types on the expansion port: * Active video (data type 15) contains component YUV 4 : 2 : 2 signal, 720 active pixels per line. The amplitude and offsets are programmable via DBRI7 to DBRI0, DCON7 to DCON0, DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and OFFV0. For nominal levels see Fig.17. * Test line (data type 6) is similar to active video format, with some constraints within the data processing: - adaptive chrominance comb filter, vertical filter (chrominance comb filter for NTSC standards, PAL phase error correction) within the chrominance processing are disabled - adaptive luminance comb filter, peaking and chrominance trap are bypassed within the luminance processing. This data type is defined for future enhancements. It could be activated for lines containing standard test signals within the vertical blanking period. Currently the most sources do not contain test lines. For nominal levels see Fig.17. * Raw samples (data types 0 to 5 and 7 to 14): UV-samples are similar to data type 6, but CVBS samples are transferred instead of processed luminance samples within the Y time slots. Table 27 Data format on the expansion port BLANKING PERIOD ... 80 TIMING REFERENCE CODE (HEX)(1) The amplitude and offset of the CVBS signal is programmable via RAWG7 to RAWG0 and RAWO7 to RAWO0; see Chapter 15 "I2C-bus description", Tables 62 and 63. For nominal levels see Fig.18. The relation of LCR programming to line numbers is described in Section 8.2, see Tables 4 to 7. The data type selections by LCR are overruled by setting OFTS2 (subaddress 13H bit 2) = 1. This setting is mainly intended for device production test. The VPO-bus carries the upper or lower 8 bits of the two ADCs dependent on OFTS[1:0]13H[1:0] settings; see Table 57. The output configuration is done via MODE[3:0]02H[3:0] settings; see Table 39. If a YC mode is selected, the expansion port carries the multiplexed output signals of both ADCs, in CVBS mode the output of only one ADC. No timing reference codes are generated in this mode. Remark: The LSBs (bit 0) of the ADCs are also available on pin RTS0. For details see Table 55. The SAV/EAV timing reference codes define start and end of valid data regions. During horizontal blanking period between EAV and SAV the ITU-blanking code sequence `- 80 - 10 - 80 - 10 -...' is transmitted. The position of the F-bit is constant according to ITU 656 (see Tables 29 and 30). The V-bit can be generated in two different ways (see Tables 29 and 30) controlled via OFTS1 and OFTS0, see Table 57. F and V bits change synchronously with the EAV code. 720 PIXELS YUV 4 : 2 : 2 DATA(2) TIMING REFERENCE CODE (HEX)(1) BLANKING PERIOD 10 ... 10 FF 00 00 SAV CB0 Y0 CR0 Y1 CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80 Notes 1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to `010', see Table 57. In this event the code sequence is replaced by the standard `- 80 - 10 -' blanking values. 2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y-samples are replaced by CVBS samples. 2000 Mar 15 63 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 28 SAV/EAV format on expansion port XPD7 to XPD0 BIT 7 1 field bit 1st field: F = 0 2nd field: F = 1 BIT 6 (F) BIT 5 (V) vertical blanking bit VBI: V = 1 active video: V = 0 format H = 0 in SAV format H = 1 in EAV format BIT 4 (H) SAA7114H BIT 3 BIT 2 BIT 1 BIT 0 (P3) (P2) (P1) (P0) reserved; evaluation not recommended (protection bits according to ITU 656) for vertical timing see Tables 29 and 30 Table 29 525 lines/60 Hz vertical timing V LINE NUMBER 1 to 3 4 to 19 20 21 22 to 261 262 263 264 and 265 266 to 282 283 284 285 to 524 525 F (ITU 656) OFTS[2:0] = 000 (ITU 656) 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 OFTS[2:0] = 001 according to selected VGATE position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 59 to 61 Table 30 625 lines/50 Hz vertical timing V LINE NUMBER 1 to 22 23 24 to 309 310 311 and 312 313 to 335 336 337 to 622 623 624 and 625 F (ITU 656) OFTS[2:0] = 000 (ITU 656) 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 OFTS[1:0] = 10 according to selected VGATE position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 59 to 61 2000 Mar 15 64 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 9.4.2 X-PORT CONFIGURED AS INPUT Available formats are: * YUV 4 : 2 : 2, * YUV 4 : 1 : 1, * Raw samples * Decoded VBI-data. SAA7114H If data input mode is selected at the expansion port, then the scaler can choose it's input data stream from the on-chip video decoder, or from expansion port (controlled by bit SCSRC[1:0]91H[5:4]). Byte serial YUV 4 : 2 : 2, or subsets for other sampling schemes, or raw samples from an external ADC may be input (see also bits FSC[2:0]91H[2:0]). The input stream must be accompanied by an external clock XCLK, qualifier XDQ and reference signals XRH and XRV. Instead of the reference signal, embedded SAV and EAV codes according to ITU 656 are also accepted. The protection bits are not evaluated. XRH and XRV carry the horizontal and vertical synchronization signals for the digital video stream through the expansion port. The field ID of the input video stream is carried in the phase (edge) of XRV and state of XRH, or directly as FS (frame sync, odd/even signal) on the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]] and XDV1[92H[5]]). The trigger events on XRH (rising/falling edge) and XRV (rising/falling/both edges) for the scalers acquisition window are defined by XDV[1:0]92H[5:4] and XDH[92H[2]]. Also the signal polarity of the qualifier can be defined (bit XDQ[92H[1]]). Alternatively to a qualifier, the input clock can be applied to a gated clock (means clock gated with a data qualifier, controlled by bit XCKS[92H[0]]). In this event, all input data will be qualified. 9.5 Image port (I-port) For handshake with the receiving VGA controller, or other memory or bus interface circuitry, F, H and V reference signals and programmable FIFO flags are provided. The information will be provided on pins IGP0, IGP1, IGPH and IGPV. The functionality on this pins is controlled via subaddresses 84H and 85H. VBI-data is collected over an entire line in its own FIFO, and transferred as an uninterrupted block of bytes. Decoded VBI-data can be signed by the VBI flag on pin IGP0/1. As scaled video data and decoded VBI-data may come from different and asynchronous sources, an arbitration scheme is needed. Normally VBI-data slicer has priority. The image port consists of the pins and/or signals, as listed in Table 31. For pin constrained applications, or interfaces, the relevant timing and data reference signals can also get encoded into the data stream. Therefore the corresponding pins do not need to get connected. The minimum image port configuration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. The inserted codes are defined in close relation to the ITU/CCIR-656 (D1) recommendation, where possible. The following deviations from "ITU 656 recommendation" are implemented at SAA7114H's image port interface: * SAV and EAV codes are only present in those lines, where data is to be transferred, i.e. active video lines, or VBI-raw samples, no codes for empty lines * There may be more or less than 720 pixels between SAV and EAV * Data content and number of clock cycles during horizontal and vertical blanking is undefined, and may be not constant * Data stream may be interleaved with not-valid data codes, 00H, but SAV and EAV 4-byte codes are not interleaved with not-valid data codes * There may be an irregular pattern of not-valid data, or IDQ, and as a result, `CB - Y - CR - Y -' is not in a fixed phase to a regular clock divider The image port transfers data from the scaler as well as from the VBI-data slicer, if so selected (maximum 33 MHz). The reference clock is available at the ICLK pin, as output, or as input (maximum 33 MHz). As output, ICLK is derived from the locked decoder or expansion port input clock. The data stream from the scaler output is normally discontinuous. Therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) flag on pin IDQ. For pin constrained applications the IDQ pin can be programmed to function as gated clock output (bit ICKS2[80H[2]]). The data formats at the image port are defined in Dwords of 32 bits (4 bytes), like the related FIFO structures. But the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are used for chrominance data. The four bytes of the Dwords are serialized in words or bytes. 2000 Mar 15 65 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler * VBI-raw sample streams are enveloped with SAV and EAV, like normal video * Decoded VBI-data is transported as Ancillary (ANC) data, two modes: - direct decoded VBI-data bytes (8-bit) are directly placed in the ANC data field, 00H and FFH codes may appear in data block (violation to CCIR-656) - recoded VBI-data bytes (8-bit) directly placed in ANC data field, 00H and FFH codes will be recoded to even parity codes 03H and FCH to suppress invalid CCIR-656 codes. Table 31 Signals dedicated to the image port SYMBOL IPD7 to IPD0 ICLK PIN 54 to 57 and 59 to 62 45 I/O I/O I-port data DESCRIPTION SAA7114H There are no empty cycles in the ancillary code and its data field. The data codes 00H and FFH are suppressed (changed to 01H or FEH respectively) in active video stream, as well as in VBI-raw sample stream (VBI pass-through). Optionally the number range can be limited further. BIT ICODE[93H[7]], ISWP[1:0]85H[7:6] and IPE[1:0]87[1:0] ICKS[1:0]80H[1:0] and IPE[1:0]87H[1:0] ICKS2[80H[2]], IDQP[85H[0]] and IPE[1:0]87H[1:0] IDH[1:0]84H[1:0], IRHP[85H[1]] and IPE[1:0]87H[1:0] IDV[1:0]84H[3:2], IRVP[85H[2]] and IPE[1:0]87H[1:0] I/O continuous reference clock at image port, can be input or output, as output decoder LLC or XCLK from X-port O data valid flag at image port, qualifier, with programmable polarity; secondary function: gated clock horizontal reference output signal, copy of the H-gate signal of the scaler, with programmable polarity; alternative functions: HRESET pulse vertical reference output signal, copy of the V-gate signal of the scaler, with programmable polarity; alternative functions: VRESET pulse general purpose output signal for I-port general purpose output signal for I-port target ready input signals port control, switches I-port into 3-state IDQ 46 IGPH 53 O IGPV 52 O IGP1 IGP0 ITRDY ITRI 49 48 42 47 O O I I IDG12[86H[4]], IDG1[1:0]84H[5:4], IG1P[85H[3]] and IPE[1:0]87H[1:0] IDG02[86H[5]], IDG0[1:0]84H[7:6], IG0P[85H[4]] and IPE[1:0]87H[1:0] - IPE[1:0]87H[1:0] 2000 Mar 15 66 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 9.6 Host port for 16-bit extension of video data I/O (H-port) SAA7114H The H-port pins HPD can be used for extension of the data I/O paths to 16-bit. Functional priority has the I-port. If I8_16[93H[6]] is set to logic 1 the output drivers of the H-port are enabled dependent on the I-port enable control. For I8_16 = 0, the HPD output is disabled. Table 32 Signals dedicated to the host port SYMBOL HPD7 to HPD0 PIN 64 to 67 and 69 to 72 I/O DESCRIPTION BIT IPE[1:0]87H[1:0], ITRI[8FH[6]] and I8_16[93H[6]] I/O 16-bit extension for digital I/O (chrominance component) 9.7 9.7.1 Basic input and output timing diagrams I-port and X-port I-PORT OUTPUT TIMING The following diagrams are sketching the output timing via the I-port. IGPH and IGPV are sketched as logic 1 active gate signals. If reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates. Valid data is accompanied by the output data qualifier on pin IDQ. In addition invalid cycles are marked with output code 00H. The IDQ output pin may be defined to be a gated clock output signal (ICLK AND internal IDQ). 9.7.2 X-PORT INPUT TIMING At the X-port the input timing requirements are the same as sketched for the I-port output. But different to this: * It is not necessary to mark invalid cycles with a 00H code * No constraints on the input qualifier (can be a random pattern) * XCLK may be a gated clock (XCLK AND external XDQ). Remark: All timings illustrated in Figs 31 to 37 are given for an uninterrupted output stream (no handshake with the external hardware). handbook, full pagewidth ICLK IDQ IPD [ 7:0 ] 00 FF 00 00 SAV 00 CB Y CR Y 00 CB Y CR Y 00 IGPH MHB550 Fig.31 Output timing I-port for serial 8-bit data at start of a line (ICODE = 1). 2000 Mar 15 67 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth ICLK IDQ IPD [ 7:0 ] 00 CB Y CR Y 00 CB Y CR Y 00 IGPH MHB551 Fig.32 Output timing I-port for serial 8-bit data at start of a line (ICODE = 0). handbook, full pagewidth ICLK IDQ IPD [ 7:0 ] 00 CB Y CR Y 00 CB Y CR Y 00 FF 00 00 EAV 00 IGPH MHB552 Fig.33 Output timing I-port for serial 8-bit data at end of a line (ICODE = 1). 2000 Mar 15 68 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth ICLK IDQ IPD [ 7:0 ] 00 CB Y CR Y 00 CB Y CR Y 00 IGPH MHB553 Fig.34 Output timing I-port for serial 8-bit data at end of a line (ICODE = 0). handbook, full pagewidth ICLK IDQ IPD [ 7:0 ] 00 FF 00 00 Y0 Y1 00 Y2 Y3 Yn - 1 Yn 00 FF 00 00 HPD [ 7:0 ] 00 00 SAV 00 CB CR 00 CB CR CB CR 00 00 EAV 00 IGPH MHB554 Fig.35 Output timing for 16-bit data output via I-port and H-port with codes (ICODE = 1), timing is like 8-bit output, but packages of 2 bytes per valid cycle. 2000 Mar 15 69 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth IDQ IGPH IGPV MHB555 Fig.36 H-gate and V-gate output timing. handbook, full pagewidth ICLK IDQ IPD [ 7:0 ] 00 00 FF FF DID SDID XX YY ZZ CS BC 00 00 00 HPD [ 7:0 ] 00 FF 00 00 SAV BC FF 00 00 EAV ISLD MHB556 Fig.37 Output timing for sliced VBI-data in 8-bit serial output mode (dotted graphs for SAV/EAV mode). 2000 Mar 15 70 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 10 BOUNDARY SCAN TEST The SAA7114H has built in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7114H follows the "IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). Table 33 BST instructions supported by the SAA7114H INSTRUCTION BYPASS EXTEST SAMPLE DESCRIPTION SAA7114H The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 33). Details about the JTAG BST-TEST can be found in the specification "IEEE Std. 1149.1". A file containing the detailed Boundary Scan Description Language (BSDL) description of the SAA7114H is available on request. This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number. This optional instruction allows testing of the internal logic (no customer support available). This private instruction allows testing by the manufacturer (no customer support available). When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Fig.38. CLAMP IDCODE INTEST USER1 10.1 Initialization of boundary scan circuit The TAP (Test Access Port) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW. 10.2 Device identification codes A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service. 2000 Mar 15 71 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth MSB 31 TDI 28 27 0111000100010100 16-bit part number 12 11 00000010101 11-bit manufacturer identification 1 LSB 0 1 TDO nnnn 4-bit version code MHB557 Fig.38 32 bits of identification code. 11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins connected together and all supply pins connected together. SYMBOL VDDD VDDA VIA VOA VID VOD VSS Tstg Tamb Tamb(bias) Vesd Notes 1. Maximum: 4.6 V. 2. Except pin XTALI. 3. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 12 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 54 UNIT K/W PARAMETER digital supply voltage analog supply voltage input voltage at analog inputs output voltage at analog output input voltage at digital inputs and outputs output voltage at digital outputs voltage difference between VSSAn and VSSDn storage temperature operating ambient temperature operating ambient temperature under bias electrostatic discharge all pins note 3 CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 outputs in 3-state; -0.5 note 2 outputs active -0.5 - -65 0 -10 MAX. +4.6 +4.6 VDDA + 0.5(1) VDDA + 0.5 +5.5 VDDD + 0.5 100 +150 70 +80 V V V V V V mV C C C V UNIT -2000 +2000 2000 Mar 15 72 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H 13 CHARACTERISTICS VDDD = 3.0 to 3.6 V; VDDA = 3.1 to 3.5 V; Tamb = 25 C; timings and levels refer to drawings and conditions illustrated in Fig.39; unless otherwise specified. SYMBOL Supplies VDDD IDDD PD VDDA IDDA digital supply voltage digital supply current power dissipation digital part analog supply voltage analog supply current AOSL1 to AOSL0 = 0 CVBS mode Y/C mode PA Ptot(A+D) Ptot(A+D)(pd) power dissipation analog part total power dissipation analog and digital part total power dissipation analog and digital part in power-down mode total power dissipation analog and digital part in power-save mode CVBS mode Y/C mode CVBS mode Y/C mode CE pulled down to ground - - - - - - - 47 72 150 240 450 540 5 - - - - - - - mA mA mW mW mW mW mW X-port 3-state; 8-bit I-port 3.0 - - 3.1 3.3 90 300 3.3 3.6 - - 3.5 V mA mW V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Ptot(A+D)(ps) I2C-bus controlled via subaddress 88H = 0FH - 75 - mW Analog part Iclamp Vi(p-p) clamping current input voltage (peak-to-peak value) VI = 0.9 V DC - 8 0.7 - - A V for normal video levels - 1 V (p-p), -3 dB termination 27/47 and AC coupling required; coupling capacitor = 22 nF clamping current off fi < 5 MHz at -3 dB 200 - - - - Zi Ci cs B diff input impedance input capacitance channel crosstalk - - - 7 2 - 10 -50 - - k pF dB 9-bit analog-to-digital converters analog bandwidth differential phase (amplifier plus anti-alias filter bypassed) differential gain (amplifier plus anti-alias filter bypassed) ADC clock frequency MHz deg Gdiff - 2 - % fclk(ADC) 12.8 - 14.3 MHz 2000 Mar 15 73 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SYMBOL LEdc(d) LEdc(i) Digital inputs VIL(SCL,SDA) VIH(SCL,SDA) VIL(XTALI) VIH(XTALI) VIL(n) VIH(n) ILI ILI/O Ci VOL(SDA) VOL(clk) VOH(clk) VOL VOH LOW-level input voltage pins SDA and SCL HIGH-level input voltage pins SDA and SCL LOW-level CMOS input voltage pin XTALI HIGH-level CMOS input voltage pin XTALI LOW-level input voltage all other inputs HIGH-level input voltage all other inputs input leakage current I/O leakage current input capacitance I/O at high impedance -0.5 0.7VDDD -0.3 2.0 -0.3 2.0 - - - - -0.5 2.4 0 2.4 - - - - - - - - - - - - - - PARAMETER DC differential linearity error DC integral linearity error CONDITIONS - - MIN. TYP. 0.7 1 - - SAA7114H MAX. UNIT LSB LSB +0.3VDDD VDDD + 0.5 +0.8 VDDD + 0.3 +0.8 5.5 1 10 8 V V V V V V A A pF Digital outputs; note 1 LOW-level output voltage pin SDA LOW-level output voltage for clocks HIGH-level output voltage for clocks LOW-level output voltage all other digital outputs HIGH-level output voltage all other digital outputs SDA at 3 mA sink current 0.4 +0.6 VDDD + 0.5 0.4 VDDD + 0.5 V V V V V Clock output timing (LLC and LLC2); note 2 CL Tcy tr tf td(LLC-LLC2) output load capacitance cycle time duty factors for tLLCH/tLLC and tLLC2H/tLLC2 rise time LLC and LLC2 fall time LLC and LLC2 delay time between LLC and LLC2 output pin LLC pin LLC2 CL = 40 pF 0.2 V to VDDD - 0.2 V VDDD - 0.2 V to 0.2 V measured at 1.5 V; CL = 25 pF 15 35 70 40 - - -4 - - - - - - - 50 39 78 60 5 5 +8 pF ns ns % ns ns ns 2000 Mar 15 74 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SYMBOL Horizontal PLL fhor(n) fhor/fhor(n) fsc(n) nominal line frequency permissible static deviation 50 Hz field 60 Hz field Subcarrier PLL nominal subcarrier frequency PAL BGHI NTSC M PAL M PAL N fsc fxtal(n) fxtal(n) fxtal(n)(T) lock-in range Crystal oscillator for 32.11 MHz; note 3 nominal frequency permissible nominal frequency deviation permissible nominal frequency deviation with temperature 3rd harmonic - - - 32.11 - - - - - - - 400 4433619 3579545 3575612 3582056 - - - - - - - - - 15625 15734 - - - PARAMETER CONDITIONS MIN. TYP. SAA7114H MAX. UNIT Hz Hz % 5.7 Hz Hz Hz Hz Hz MHz 10-6 70 x 30 x 10-6 CRYSTAL SPECIFICATION (Y1) Tamb(X1) CL Rs C1 C0 fxtal(n) fxtal(n) fxtal(n)(T) operating ambient temperature load capacitance series resonance resistor motional capacitance parallel capacitance 0 8 - - - 3rd harmonic - - - - - 40 1.5 20% 4.3 20% 24.576 - - 70 - 80 - - - 50 x 10-6 C pF fF pF Crystal oscillator for 24.576 MHz; note 3 nominal frequency permissible nominal frequency deviation permissible nominal frequency deviation with temperature MHz 20 x 10-6 CRYSTAL SPECIFICATION (Y1) Tamb(X1) CL Rs C1 operating ambient temperature load capacitance series resonance resistor motional capacitance 0 8 - - - - 40 1.5 20% 70 - 80 - C pF fF 2000 Mar 15 75 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SYMBOL C0 Tcy tr tf tSU;DAT tHD;DAT CL Tcy tr tf PARAMETER parallel capacitance CONDITIONS - 31 40 - - - - 15 35 35 0.6 to 2.6 V 2.6 to 0.6 V - - MIN. TYP. 3.5 20% - 50 - - 10 3 - - - - - - SAA7114H MAX. UNIT pF Clock input timing (XCLK) cycle time duty factors for tLLCH/tLLC rise time fall time 45 60 5 5 - - 50 39 65 5 5 ns % ns ns Data and control signal input timing X-port, related to XCLK input input data set-up time input data hold time ns ns Clock output timing output load capacitance cycle time duty factors for tXCLKH/tXCLKL rise time fall time pF ns % ns ns Data and control signal output timing X-port, related to XCLK output (for XPCK[1:0]83H[5:4] = 00 is default); note 2 CL tOHD;DAT tPD output load capacitance output data hold time propagation delay from positive edge of XCLK output fall time CL = 15 pF CL = 15 pF 15 - - - 14 24 50 - - pF ns ns tf CL tOHD;DAT tPD - 15 CL = 15 pF CL = 15 pF - - - - 14 24 ns Control signal output timing RT port, related to LLC output output load capacitance output hold time propagation delay from positive edge of LLC output fall time 50 - - pF ns ns tf CL Tcy tr - 15 31 35 0.6 to 2.6 V - - - - - - ns ICLK output timing output load capacitance cycle time duty factors for tICLKH/tICLKL rise time 50 45 65 5 pF ns % ns 2000 Mar 15 76 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SYMBOL tf CL tOHD;DAT to(d) tdis ten PARAMETER fall time CONDITIONS 2.6 to 0.6 V - 15 CL = 15 pF CL = 15 pF CL = 25 pF - - - - MIN. - - 12 22 - - TYP. 5 SAA7114H MAX. UNIT ns Data and control signal output timing I-port, related to ICLK output (for IPCK[1:0]87H[5:4] = 00 is default) output load capacitance at all outputs output data hold time output delay time port enable time from 3-state 50 - - port disable time to 3-state CL = 25 pF ICLK input timing Tcy tL, tH tr CL tOHD;DAT to(d) tdis ten Notes 1. The levels must be measured with load circuits; 1.2 k at 3 V (TTL load); CL = 50 pF. 2. The effects of rise and fall times are included in the calculation of tOHD;DAT and tPD. Timings and levels refer to drawings and conditions illustrated in Fig.39. 3. The crystal oscillator drive level is typical 0.28 mW. cycle time LOW and HIGH times rise time 31 - - Data and control signal output timing I-port, related to ICLK input (for ICKS[1:0]80H[1:0] = 11) output load capacitance at all outputs output data hold time output delay time port enable time from 3-state port disable time to 3-state CL = 25 pF 2000 Mar 15 77 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth Tcy t XCLKH 2.4 V clock input XCLK 1.5 V 0.6 V t SU;DAT t HD;DAT tf tr data and control inputs (X port) 2.0 V not valid 0.8 V t SU;DAT t HD;DAT 2.0 V input XDQ 0.8 V t o(d) t OHD;DAT data and control outputs X port, I port -2.4 V -0.6 V t X(I)CLKH clock outputs XCLK, ICLK and ICLK-input t X(I)CLKL -2.6 V -1.5 V -0.6 V tf tr MHB569 Fig.39 Data input/output timing diagram (X-port, RT port and I-port). 2000 Mar 15 78 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Mar 15 79 14 APPLICATION INFORMATION Philips Semiconductors handbook, full pagewidth PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler HPD0 HPD1 HPD2 HPD3 HPD4 HPD5 HPD6 L3 2.2 H 3.3 V (A) TDO TDI BST[2:0] BST0 BST1 BST2 BST2 R24 0 Place 0 if BST is not used HPD7 V DD(3.3) V DDA(3.3) L2 2.2 H 3.3 V (D) HPDL[7:0] SCL TP3 TP2 TP4 R17 0 AOUT SDA VDDDE1 VDDDE2 VDDDE3 VDDDE4 VDDDI1 VDDDI2 VDDDI3 VDDDI4 VDDDI5 VDDDI6 VDDA0 VDDA1 VDDA2 TEST3 TEST4 TEST5 VDDX TRST TMS TDO TCK DGND TDI AOUT HPD0 HPD1 HPD2 HPD3 HPD4 HPD5 HPD6 HPD7 SDA SCL 98 99 97 3 AI24 R5 18 AI23 R3 18 AI22 R2 18 AI21 R4 18 C17 47 nF C14 AI23 47 nF C15 47 nF C16 AI21 47 nF C25 47 nF AGND AI12 R1 18 C18 47 nF C19 R6 18 AI11 AGND 3.3 V (D) R14 3.3 k R7 56 R8 56 R9 56 R10 56 R11 56 R12 56 47 nF C26 AI1D 47 nF AGND 27 CE AI11 20 AI12 18 16 AI22 14 12 AI24 2 23 17 11 1 25 51 75 33 43 58 68 83 93 8 72 71 70 69 67 66 65 64 77 78 79 31 32 22 54 55 IPDL[7:0] IPD7 IPD6 IPD5 IPD4 IPD3 IPD2 IPD1 IPD0 ITRDY ICLK IDQ ITRI IGP0 IGP1 IGPV IGPH AMCLK ASCLK ALRCLK AMXCLK R20 open 6 XTALO XTALI L1 10 H 24.576 MHz Y1 R18 0 R21 open R22 open ACLK IPD7 IPD6 IPD5 IPD4 IPD3 IPD2 IPD1 IPD0 IMCON7 IMCON6 IMCON5 IMCON4 IMCON3 IMCON2 IMCON1 IMCON0 R15 3.3 k Strapping clock frequency DGND R13 open 3.3 V (D) IMCON[7:0] 10 56 57 59 60 61 62 42 45 SAA7114H AI2D 13 46 47 48 49 52 53 37 39 40 41 19 24 15 9 21 VSSA0 VSSA1 VSSA2 AGND 26 50 76 100 5 88 63 38 VSSDE1 VSSDE2 VSSDE3 VSSDE4 VSSX VSSDI3 VSSDI2 VSSDI1 28 29 LLC2 LLC 30 RES 36 35 34 44 73 74 RTCO TEST0 TEST1 TEST2 RTS1 RTS0 81 82 84 85 86 87 89 90 XPD7 XPD6 XPD5 XPD4 XPD3 XPD2 XPD1 XPD0 92 91 96 95 94 80 4 XRDY XTOUT XRH XRV XDQ XCLK XTRI 7 C22 1 nF C20 10 pF C21 10 pF XCON0 XCON1 XCON2 XCON3 XCON4 XCON5 XPD7 XPD6 XPD5 XPD4 XPD3 XPD2 XPD1 AGND DGND XPD0 TP1 TP5 TP7 TP6 XCON6 CE DGND XCON[7:0] XPD[7:0] LLC RTS0 RTS1 Preliminary specification Strapping I2C-bus slave address R19 open 3.3 V (D) C24 10 F C9 100 nF C7 100 nF C2 100 nF C3 100 nF C4 100 nF C5 100 nF C6 100 nF C12 100 nF C10 100 nF C11 100 nF R23 3.3 k C13 100 nF C8 100 nF C1 100 nF C23 10 F 3.3 V (A) RTCO RESON MHB527 SAA7114H R16 0 DGND AGND Fig.40 Application example with 24.576 MHz crystal. Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook, full pagewidth quartz (3rd harmonic) 24.576 MHz XTAL C 10 pF XTALI 6 XTAL 6 SAA7114H 7 XTALI 7 SAA7114H L 10 H 20% C 10 pF C 1 nF MHB558 a. With quartz crystal. b. With external clock. Fig.41 Oscillator application. 15 I2C-BUS DESCRIPTION The SAA7114H supports the `fast mode' I2C-bus specification extension (data rate up to 400 kbits/s). 15.1 I2C-bus format handbook, full pagewidth S SLAVE ADDRESS W ACK-s SUBADDRESS ACK-s DATA data transferred (n bytes + acknowledge) ACK-s P MHB339 a. Write procedure. handbook, full pagewidth S Sr SLAVE ADDRESS W SLAVE ADDRESS R ACK-s ACK-s SUBADDRESS DATA ACK-s ACK-m P data transferred (n bytes + acknowledge) MHB340 b. Read procedure (combined). Fig.42 I2C-bus format. 2000 Mar 15 80 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 34 Description of I2C-bus format CODE S Sr Slave address W Slave address R ACK-s ACK-m Subaddress Data P X Note 1. If pin RTCO strapped to ground via a 3.3 k resistor. Table 35 Subaddress description and access SUBADDRESS 00H F0H to FFH chip version reserved DESCRIPTION START condition repeated START condition `0100 0010' (= 42H, default) or `0100 0000' (= 40H; note 1) `0100 0011' (= 43H, default) or `0100 0001' (= 41H; note 1) acknowledge generated by the slave acknowledge generated by the master subaddress byte; see Tables 35 and 36 DESCRIPTION SAA7114H data byte; see Table 36; if more than one byte DATA is transmitted the subaddress pointer is automatically incremented STOP condition read/write control bit (LSB slave address); X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter) ACCESS (READ/WRITE) read only - read and write read and write - read only - read and write - read and write read only - read and write read and write read and write Video decoder: 01H to 2FH 01H to 05H 06H to 19H 1AH to 1EH 1FH 20H to 2FH front-end part decoder part reserved video decoder status byte reserved Audio clock generation: 30H to 3FH 30H to 3AH 3BH to 3FH audio clock generator reserved General purpose VBI-data slicer: 40H to 7FH 40H to 60H 61H to 62H 64H to 7FH VBI-data slicer VBI-data slicer status reserved X-port, I-port and the scaler: 80H to EFH 80H to 8FH 90H to BFH C0H to EFH task independent global settings task A definition task B definition 2000 Mar 15 81 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 36 I2C-bus receiver/transmitter overview 2000 Mar 15 82 Philips Semiconductors PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler REGISTER FUNCTION Chip version: register 00H Chip version (read only) SUB ADDR. (HEX) D7 D6 D5 D4 D3 D2 D1 D0 00 ID07 ID06 ID05 ID04 - - - - Video decoder: registers 01H to 2FH FRONT-END PART: REGISTERS 01H TO 05H Horizontal increment delay Analog input control 1 Analog input control 2 Analog input control 3 Analog input control 4 01 02 03 04 05 (1) (1) (1) (1) IDEL3 MODE3 HOLDG GAI13 GAI23 IDEL2 MODE2 GAFIX GAI12 GAI22 IDEL1 MODE1 GAI28 GAI11 GAI21 IDEL0 MODE0 GAI18 GAI10 GAI20 FUSE1 (1) FUSE0 HLNRS GAI16 GAI26 GUDL1 VBSL GAI15 GAI25 GUDL0 WPOFF GAI14 GAI24 GAI17 GAI27 DECODER PART: REGISTERS 06H TO 2FH Horizontal sync start Horizontal sync stop Sync control Luminance control Luminance brightness control Luminance contrast control Chrominance saturation control Chrominance hue control Chrominance control 1 Chrominance gain control Chrominance control 2 Mode/delay control RT signal control RT/X-port output control Analog/ADC/compatibility control VGATE start, FID change VGATE stop Miscellaneous/VGATE MSBs 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 HSB7 HSS7 AUFD BYPS DBRI7 DCON7 DSAT7 HUEC7 CDTO ACGC OFFU1 COLO RTSE13 RTCE CM99 VSTA7 VSTO7 LLCE HSB6 HSS6 FSEL YCOMB DBRI6 DCON6 DSAT6 HUEC6 CSTD2 CGAIN6 OFFU0 RTP1 RTSE12 XRHS UPTCV VSTA6 VSTO6 LLC2E HSB5 HSS5 FOET LDEL DBRI5 DCON5 DSAT5 HUEC5 CSTD1 CGAIN5 OFFV1 HDEL1 RTSE11 XRVS1 AOSL1 VSTA5 VSTO5 (1) HSB4 HSS4 HTC1 LUBW DBRI4 DCON4 DSAT4 HUEC4 CSTD0 CGAIN4 OFFV0 HDEL0 RTSE10 XRVS0 AOSL0 VSTA4 VSTO4 (1) HSB3 HSS3 HTC0 LUFI3 DBRI3 DCON3 DSAT3 HUEC3 DCVF CGAIN3 CHBW RTP0 RTSE03 HLSEL XTOUTE VSTA3 VSTO3 (1) HSB2 HSS2 HPLL LUFI2 DBRI2 DCON2 DSAT2 HUEC2 FCTC CGAIN2 LCBW2 YDEL2 RTSE02 OFTS2 OLDSB VSTA2 VSTO2 VGPS HSB1 HSS1 VNOI1 LUFI1 DBRI1 DCON1 DSAT1 HUEC1 (1) HSB0 HSS0 VNOI0 LUFI0 DBRI0 DCON0 DSAT0 HUEC0 CCOMB CGAIN0 LCBW0 YDEL0 RTSE00 OFTS0 APCK0 VSTA0 VSTO0 VSTA8 CGAIN1 LCBW1 YDEL1 RTSE01 OFTS1 APCK1 VSTA1 VSTO1 VSTO8 Preliminary specification SAA7114H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Mar 15 83 Philips Semiconductors SUB ADDR. (HEX) 18 19 1A to 1E 1F 1F 20 to 2F PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler REGISTER FUNCTION Raw data gain control Raw data offset control Reserved Status byte video decoder (read only, OLDSB = 0) Status byte video decoder (read only, OLDSB = 1) Reserved D7 RAWG7 RAWO7 (1) D6 RAWG6 RAWO6 (1) D5 RAWG5 RAWO5 (1) D4 RAWG4 RAWO4 (1) D3 RAWG3 RAWO3 (1) D2 RAWG2 RAWO2 (1) D1 RAWG1 RAWO1 (1) D0 RAWG0 RAWO0 (1) INTL INTL (1) HLVLN HLCK (1) FIDT FIDT (1) GLIMT GLIMT (1) GLIMB GLIMB (1) WIPA WIPA (1) COPRO SLTCA (1) RDCAP CODE (1) Audio clock generator part: registers 30H to 3FH Audio master clock cycles per field 30 31 32 Reserved Audio master clock nominal increment 33 34 35 36 Reserved Clock ratio AMCLK to ASCLK Clock ratio ASCLK to ALRCLK Audio clock control Reserved 37 38 39 3A 3B to 3F ACPF7 ACPF15 (1) (1) ACPF6 ACPF14 (1) (1) ACPF5 ACPF13 (1) (1) ACPF4 ACPF12 (1) (1) ACPF3 ACPF11 (1) (1) ACPF2 ACPF10 (1) (1) ACPF1 ACPF9 ACPF17 (1) ACPF0 ACPF8 ACPF16 (1) ACNI7 ACNI15 (1) (1) (1) (1) (1) (1) ACNI6 ACNI14 (1) (1) (1) (1) (1) (1) ACNI5 ACNI13 ACNI21 (1) ACNI4 ACNI12 ACNI20 (1) ACNI3 ACNI11 ACNI19 (1) ACNI2 ACNI10 ACNI18 (1) ACNI1 ACNI9 ACNI17 (1) ACNI0 ACNI8 ACNI16 (1) SDIV5 LRDIV5 (1) (1) SDIV4 LRDIV4 (1) (1) SDIV3 LRDIV3 APLL (1) SDIV2 LRDIV2 AMVR (1) SDIV1 LRDIV1 LRPH (1) SDIV0 LRDIV0 SCPH (1) General purpose VBI-data slicer part: registers 40H to 7FH Slicer control 1 LCR2 to LCR24 (n = 2 to 24) Programmable framing code Horizontal offset for slicer Vertical offset for slicer Field offset and MSBs for horizontal and vertical offset Reserved (for testing) 40 41 to 57 58 59 5A 5B 5C (1) HAM_N LCRn_6 FC6 HOFF6 VOFF6 RECODE (1) FCE LCRn_5 FC5 HOFF5 VOFF5 (1) HUNT_N LCRn_4 FC4 HOFF4 VOFF4 VOFF8 (1) (1) (1) (1) (1) LCRn_7 FC7 HOFF7 VOFF7 FOFF (1) LCRn_3 FC3 HOFF3 VOFF3 (1) LCRn_2 FC2 HOFF2 VOFF2 HOFF10 (1) LCRn_1 FC1 HOFF1 VOFF1 HOFF9 (1) LCRn_0 FC0 HOFF0 VOFF0 HOFF8 (1) Preliminary specification SAA7114H (1) (1) This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Mar 15 84 Philips Semiconductors SUB ADDR. (HEX) 5D 5E 5F 60 61 62 63 to 7F PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler REGISTER FUNCTION Header and data identification (DID) code control Sliced data identification (SDID) code Reserved Slicer status byte 0 (read only) Slicer status byte 1 (read only) Slicer status byte 2 (read only) Reserved D7 FVREF (1) D6 (1) D5 DID5 SDID5 (1) D4 DID4 SDID4 (1) D3 DID3 SDID3 (1) D2 DID2 SDID2 (1) D1 DID1 SDID1 (1) D0 DID0 SDID0 (1) (1) (1) (1) - - LN3 (1) FC8V - LN2 (1) FC7V F21_N LN1 (1) VPSV LN8 LN0 (1) PPV LN7 DT3 (1) CCV LN6 DT2 (1) - LN5 DT1 (1) - LN4 DT0 (1) X-port, I-port and the scaler part: registers 80H to EFH TASK INDEPENDENT GLOBAL SETTINGS: 80H TO 8FH Global control 1 Reserved X-port I/O enable and output clock phase control I-port signal definitions I-port signal polarities I-port FIFO flag control and arbitration I-port I/O enable, output clock and gated clock phase control Power save control Reserved Status information scaler part 80 81 and 82 83 84 85 86 87 88 89 to 8E 8F (1) (1) SMOD (1) TEB (1) TEA (1) ICKS3 (1) ICKS2 (1) ICKS1 (1) ICKS0 (1) (1) (1) XPCK1 IDG11 ILLV IDG02 IPCK1 SWRST (1) XPCK0 IDG10 IG0P IDG12 IPCK0 DPROG (1) (1) XRQT IDV0 IRVP FFL0 (1) XPE1 IDH1 IRHP FEL1 IPE1 SLM1 (1) XPE0 IDH0 IDQP FEL0 IPE0 SLM0 (1) IDG01 ISWP1 VITX1 IPCK3 CH4EN (1) IDG00 ISWP0 VITX0 IPCK2 CH2EN (1) IDV1 IG1P FFL1 (1) SLM3 (1) (1) (1) XTRI ITRI FFIL FFOV PRDON ERR_OF FIDSCI FIDSCO Preliminary specification TASK A DEFINITION: REGISTERS 90H TO BFH SAA7114H Basic settings and acquisition window definition Task handling control X-port formats and configuration X-port input reference signal definition 90 91 92 CONLH CONLV XFDV OFIDC HLDFV XFDH FSKP2 SCSRC1 XDV1 FSKP1 SCSRC0 XDV0 FSKP0 SCRQE XCODE RPTSK FSC2 XDH STRC1 FSC1 XDQ STRC0 FSC0 XCKS This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Mar 15 85 Philips Semiconductors SUB ADDR. (HEX) 93 94 95 Horizontal input window length Vertical input window start Vertical input window length Horizontal output window length Vertical output window length 96 97 98 99 9A 9B 9C 9D 9E 9F PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler REGISTER FUNCTION I-port format and configuration Horizontal input window start D7 ICODE XO7 (1) D6 I8_16 XO6 (1) D5 FYSK XO5 (1) D4 FOI1 XO4 (1) D3 FOI0 XO3 XO11 XS3 XS11 YO3 YO11 YS3 YS11 XD3 XD11 YD3 YD11 D2 FSI2 XO2 XO10 XS2 XS10 YO2 YO10 YS2 YS10 XD2 XD10 YD2 YD10 D1 FSI1 XO1 XO9 XS1 XS9 YO1 YO9 YS1 YS9 XD1 XD9 YD1 YD9 D0 FSI0 XO0 XO8 XS0 XS8 YO0 YO8 YS0 YS8 XD0 XD8 YD0 YD8 XS7 (1) XS6 (1) XS5 (1) XS4 (1) YO7 (1) YO6 (1) YO5 (1) YO4 (1) YS7 (1) YS6 (1) YS5 (1) YS4 (1) XD7 (1) XD6 (1) XD5 (1) XD4 (1) YD7 (1) YD6 (1) YD5 (1) YD4 (1) FIR filtering and prescaling Horizontal prescaling Accumulation length Prescaler DC gain and FIR prefilter control Reserved Luminance brightness setting Luminance contrast setting Chrominance saturation setting Reserved A0 A1 A2 A3 A4 A5 A6 A7 (1) (1) (1) (1) XPSC5 XACL5 PFY1 (1) XPSC4 XACL4 PFY0 (1) XPSC3 XACL3 XC2_1 (1) XPSC2 XACL2 XDCG2 (1) XPSC1 XACL1 XDCG1 (1) XPSC0 XACL0 XDCG0 (1) PFUV1 (1) PFUV0 (1) BRIG7 CONT7 SATN7 (1) BRIG6 CONT6 SATN6 (1) BRIG5 CONT5 SATN5 (1) BRIG4 CONT4 SATN4 (1) BRIG3 CONT3 SATN3 (1) BRIG2 CONT2 SATN2 (1) BRIG1 CONT1 SATN1 (1) BRIG0 CONT0 SATN0 (1) Horizontal phase scaling Horizontal luminance scaling increment Horizontal luminance phase offset Reserved A8 A9 AA AB XSCY7 (1) Preliminary specification XSCY6 (1) XSCY5 (1) XSCY4 XSCY12 XPHY4 (1) XSCY3 XSCY11 XPHY3 (1) XSCY2 XSCY10 XPHY2 (1) XSCY1 XSCY9 XPHY1 (1) XSCY0 SAA7114H XSCY8 XPHY0 (1) XPHY7 (1) XPHY6 (1) XPHY5 (1) This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Mar 15 86 Philips Semiconductors SUB ADDR. (HEX) AC AD AE AF PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler REGISTER FUNCTION Horizontal chrominance scaling increment Horizontal chrominance phase offset Reserved D7 XSCC7 (1) D6 XSCC6 (1) D5 XSCC5 (1) D4 XSCC4 XSCC12 XPHC4 (1) D3 XSCC3 XSCC11 XPHC3 (1) D2 XSCC2 XSCC10 XPHC2 (1) D1 XSCC1 XSCC9 XPHC1 (1) D0 XSCC0 XSCC8 XPHC0 (1) XPHC7 (1) XPHC6 (1) XPHC5 (1) Vertical scaling Vertical luminance scaling increment Vertical chrominance scaling increment Vertical scaling mode control Reserved Vertical chrominance phase offset `00' Vertical chrominance phase offset `01' Vertical chrominance phase offset `10' Vertical chrominance phase offset `11' Vertical luminance phase offset `00' Vertical luminance phase offset `01' Vertical luminance phase offset `10' Vertical luminance phase offset `11' B0 B1 B2 B3 B4 B5 to B7 B8 B9 BA BB BC BD BE BF YSCY7 YSCY15 YSCC7 YSCC15 (1) (1) YSCY6 YSCY14 YSCC6 YSCC14 (1) (1) YSCY5 YSCY13 YSCC5 YSCC13 (1) (1) YSCY4 YSCY12 YSCC4 YSCC12 YMIR (1) YSCY3 YSCY11 YSCC3 YSCC11 (1) (1) YSCY2 YSCY10 YSCC2 YSCC10 (1) (1) YSCY1 YSCY9 YSCC1 YSCC9 (1) (1) YSCY0 YSCY8 YSCC0 YSCC8 YMODE (1) YPC07 YPC17 YPC27 YPC37 YPY07 YPY17 YPY27 YPY37 YPC06 YPC16 YPC26 YPC36 YPY06 YPY16 YPY26 YPY36 YPC05 YPC15 YPC25 YPC35 YPY05 YPY15 YPY25 YPY35 YPC04 YPC14 YPC24 YPC34 YPY04 YPY14 YPY24 YPY34 YPC03 YPC13 YPC23 YPC33 YPY03 YPY13 YPY23 YPY33 YPC02 YPC12 YPC22 YPC32 YPY02 YPY12 YPY22 YPY32 YPC01 YPC11 YPC21 YPC31 YPY01 YPY11 YPY21 YPY31 YPC00 YPC10 YPC20 YPC30 YPY00 YPY10 YPY20 YPY30 Preliminary specification SAA7114H TASK B DEFINITION REGISTERS C0H TO EFH Basic settings and acquisition window definition Task handling control C0 CONLH OFIDC FSKP2 FSKP1 FSKP0 RPTSK STRC1 STRC0 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Mar 15 87 Philips Semiconductors SUB ADDR. (HEX) C1 C2 C3 C4 C5 Horizontal input window length Vertical input window start Vertical input window length Horizontal output window length Vertical output window length C6 C7 C8 C9 CA CB CC CD CE CF PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler REGISTER FUNCTION X-port formats and configuration Input reference signal definition I-port format and configuration Horizontal input window start D7 CONLV XFDV ICODE XO7 (1) D6 HLDFV XFDH I8_16 XO6 (1) D5 SCSRC1 XDV1 FYSK XO5 (1) D4 SCSRC0 XDV0 FOI1 XO4 (1) D3 SCRQE XCODE FOI0 XO3 XO11 XS3 XS11 YO3 YO11 YS3 YS11 XD3 XD11 YD3 YD11 D2 FSC2 XDH FSI2 XO2 XO10 XS2 XS10 YO2 YO10 YS2 YS10 XD2 XD10 YD2 YD10 D1 FSC1 XDQ FSI1 XO1 XO9 XS1 XS9 YO1 YO9 YS1 YS9 XD1 XD9 YD1 YD9 D0 FSC0 XCKS FSI0 XO0 XO8 XS0 XS8 YO0 YO8 YS0 YS8 XD0 XD8 YD0 YD8 XS7 (1) XS6 (1) XS5 (1) XS4 (1) YO7 (1) YO6 (1) YO5 (1) YO4 (1) YS7 (1) YS6 (1) YS5 (1) YS4 (1) XD7 (1) XD6 (1) XD5 (1) XD4 (1) YD7 (1) YD6 (1) YD5 (1) YD4 (1) FIR filtering and prescaling Horizontal prescaling Accumulation length Prescaler DC gain and FIR prefilter control Reserved Luminance brightness setting Luminance contrast setting Chrominance saturation setting Reserved D0 D1 D2 D3 D4 D5 D6 D7 (1) (1) (1) (1) XPSC5 XACL5 PFY1 (1) XPSC4 XACL4 PFY0 (1) XPSC3 XACL3 XC2_1 (1) XPSC2 XACL2 XDCG2 (1) XPSC1 XACL1 XDCG1 (1) XPSC0 XACL0 XDCG0 (1) PFUV1 (1) PFUV0 (1) BRIG7 CONT7 SATN7 (1) BRIG6 CONT6 SATN6 (1) BRIG5 CONT5 SATN5 (1) BRIG4 CONT4 SATN4 (1) BRIG3 CONT3 SATN3 (1) BRIG2 CONT2 SATN2 (1) BRIG1 CONT1 SATN1 (1) BRIG0 CONT0 SATN0 (1) Preliminary specification SAA7114H Horizontal phase scaling Horizontal luminance scaling increment Horizontal luminance phase offset D8 D9 DA XSCY7 (1) XSCY6 (1) XSCY5 (1) XSCY4 XSCY12 XPHY4 XSCY3 XSCY11 XPHY3 XSCY2 XSCY10 XPHY2 XSCY1 XSCY9 XPHY1 XSCY0 XSCY8 XPHY0 XPHY7 XPHY6 XPHY5 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Mar 15 88 Philips Semiconductors SUB ADDR. (HEX) DB DC DD DE DF PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler REGISTER FUNCTION Reserved Horizontal chrominance scaling increment Horizontal chrominance phase offset Reserved D7 (1) D6 (1) D5 (1) D4 (1) D3 (1) D2 (1) D1 (1) D0 (1) XSCC7 (1) XSCC6 (1) XSCC5 (1) XSCC4 XSCC12 XPHC4 (1) XSCC3 XSCC11 XPHC3 (1) XSCC2 XSCC10 XPHC2 (1) XSCC1 XSCC9 XPHC1 (1) XSCC0 XSCC8 XPHC0 (1) XPHC7 (1) XPHC6 (1) XPHC5 (1) Vertical scaling Vertical luminance scaling increment Vertical chrominance scaling increment Vertical scaling mode control Reserved Vertical chrominance phase offset `00' Vertical chrominance phase offset `01' Vertical chrominance phase offset `10' Vertical chrominance phase offset `11' Vertical luminance phase offset `00' Vertical luminance phase offset `01' Vertical luminance phase offset `10' Vertical luminance phase offset `11' Note 1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. E0 E1 E2 E3 E4 E5 to E7 E8 E9 EA EB EC ED EE EF YSCY7 YSCY15 YSCC7 YSCC15 (1) (1) YSCY6 YSCY14 YSCC6 YSCC14 (1) (1) YSCY5 YSCY13 YSCC5 YSCC13 (1) (1) YSCY4 YSCY12 YSCC4 YSCC12 YMIR (1) YSCY3 YSCY11 YSCC3 YSCC11 (1) (1) YSCY2 YSCY10 YSCC2 YSCC10 (1) (1) YSCY1 YSCY9 YSCC1 YSCC9 (1) (1) YSCY0 YSCY8 YSCC0 YSCC8 YMODE (1) YPC07 YPC17 YPC27 YPC37 YPY07 YPY17 YPY27 YPY37 YPC06 YPC16 YPC26 YPC36 YPY06 YPY16 YPY26 YPY36 YPC05 YPC15 YPC25 YPC35 YPY05 YPY15 YPY25 YPY35 YPC04 YPC14 YPC24 YPC34 YPY04 YPY14 YPY24 YPY34 YPC03 YPC13 YPC23 YPC33 YPY03 YPY13 YPY23 YPY33 YPC02 YPC12 YPC22 YPC32 YPY02 YPY12 YPY22 YPY32 YPC01 YPC11 YPC21 YPC31 YPY01 YPY11 YPY21 YPY31 YPC00 YPC10 YPC20 YPC30 YPY00 YPY10 YPY20 Preliminary specification SAA7114H YPY30 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2 15.2.1 I2C-bus details SUBADDRESS 00H SAA7114H Table 37 Chip Version (CV) identification; 00H[7:4]; read only register LOGIC LEVELS FUNCTION ID07 Chip Version (CV) 15.2.2 SUBADDRESS 01H CV0 ID06 CV1 ID05 CV2 ID04 CV3 The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position only. Table 38 Horizontal increment delay; 01H[3:0] FUNCTION No update Minimum delay Recommended position Maximum delay 15.2.3 SUBADDRESS 02H IDEL3 1 1 1 0 IDEL2 1 1 0 0 IDEL1 1 1 0 0 IDEL0 1 0 0 0 Table 39 Analog input control 1 (AICO1); 02H[7:0] BIT DESCRIPTION SYMBOL FUSE[1:0] VALUE 00 01 10 11 D[5:4] update hysteresis for 9-bit gain (see Fig.7) GUDL[1:0] 00 01 10 11 amplifier active amplifier plus anti-alias filter active off 1 LSB 2 LSB 3 LSB FUNCTION amplifier plus anti-alias filter bypassed D[7:6] analog function select (see Fig.6) 2000 Mar 15 89 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler BIT DESCRIPTION SYMBOL MODE[3:0] VALUE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1111 Note FUNCTION SAA7114H D[3:0] mode selection Mode 0: CVBS (automatic gain) from AI11 (pin 20); see Fig. 43 Mode 1: CVBS (automatic gain) from AI12 (pin 18); see Fig. 44 Mode 2: CVBS (automatic gain) from AI21 (pin 16); see Fig. 45 Mode 3: CVBS (automatic gain) from AI22 (pin 14); see Fig. 46 Mode 4: CVBS (automatic gain) from AI23 (pin 12); see Fig. 47 Mode 5: CVBS (automatic gain) from AI24 (pin 10); see Fig. 48 Mode 6: Y (automatic gain) from AI11 (pin 20) + C (gain adjustable via GAI28 to GAI20) from AI21 (pin 16); note 1; see Fig. 49 Mode 7: Y (automatic gain) from AI12 (pin 18) + C (gain adjustable via GAI28 to GAI20) from AI22 (pin 14); note 1; see Fig. 50 Mode 8: Y (automatic gain) from AI11 (pin 20) + C (gain adapted to Y gain) from AI21 (pin 16); note 1; see Fig. 51 Mode 9: Y (automatic gain) from AI12 (pin 18) + C (gain adapted to Y gain) from AI22 (pin 14); note 1; see Fig. 52 Modes 10 to 15: reserved 1. To take full advantage of the Y/C-modes 6 to 9 the I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). handbook,AI24 halfpage handbook, AI24 halfpage AI23 AI22 AI21 AI12 AI11 AD2 CHROMA AI23 AI22 AI21 AI12 AI11 AD2 CHROMA AD1 LUMA MHB559 AD1 LUMA MHB560 Fig.43 Mode 0; CVBS (automatic gain). Fig.44 Mode 1; CVBS (automatic gain). handbook,AI24 halfpage handbook,AI24 halfpage AI23 AI22 AI21 AI12 AI11 AD2 CHROMA AI23 AI22 AI21 AI12 AI11 AD2 CHROMA AD1 LUMA MHB561 AD1 LUMA MHB562 Fig.45 Mode 2; CVBS (automatic gain). Fig.46 Mode 3; CVBS (automatic gain). 2000 Mar 15 90 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H handbook,AI24 halfpage handbook,AI24 halfpage AI23 AI22 AI21 AI12 AI11 AD2 CHROMA AI23 AI22 AI21 AI12 AI11 AD2 CHROMA AD1 LUMA MHB563 AD1 LUMA MHB564 Fig.47 Mode 4; CVBS (automatic gain). Fig.48 Mode 5; CVBS (automatic gain). handbook,AI24 halfpage handbook,AI24 halfpage AI23 AI22 AI21 AI12 AI11 I2C-bus AD2 CHROMA AI23 AI22 AI21 AI12 AI11 I2C-bus AD2 CHROMA AD1 LUMA MHB565 AD1 LUMA MHB566 bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). Fig.49 Mode 6; Y + C (gain channel 2 adjusted via GAI2). Fig.50 Mode 7; Y + C (gain channel 2 adjusted via GAI2). handbook,AI24 halfpage handbook,AI24 halfpage AI23 AI22 AI21 AI12 AI11 AD2 CHROMA AI23 AI22 AI21 AI12 AI11 AD2 CHROMA AD1 LUMA MHB567 AD1 LUMA MHB568 I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). Fig.51 Mode 8; Y + C (gain channel 2 adapted to Y gain). 2000 Mar 15 91 Fig.52 Mode 9; Y + C (gain channel 2 adapted to Y gain). Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.4 SUBADDRESS 03H SAA7114H Table 40 Analog input control 2 (AICO2); 03H[6:0] BIT DESCRIPTION SYMBOL VALUE HLNRS VBSL 0 1 D5 AGC hold during vertical blanking period 0 1 FUNCTION normal clamping if decoder is in unlocked state reference select if decoder is in unlocked state short vertical blanking (AGC disabled during equalization and serration pulses) long vertical blanking (AGC disabled from start of pre-equalization pulses until start of active video (line 22 for 60 Hz, line 24 for 50 Hz) white peak control active white peak off AGC active AGC integration hold (freeze) automatic gain controlled by MODE3 to MODE0 gain is user programmable via GAI[17:10] and GAI[27:20] see Table 42 see Table 41 D6 HL not reference select D4 white peak off D3 automatic gain control integration D2 gain control fix D1 static gain control channel 2 sign bit D0 static gain control channel 1 sign bit 15.2.5 SUBADDRESS 04H WPOFF HOLDG GAFIX GAI28 GAI18 0 1 0 1 0 1 Table 41 Analog input control 3 (AICO3): static gain control channel 1; 03H[0] and 04H[7:0] DECIMAL VALUE 0... ...144 145... ...511 15.2.6 GAIN (dB) -3 0 0 +6 SIGN BIT 03H[0] GAI18 0 0 0 1 GAI17 0 1 1 1 GAI16 0 0 0 1 CONTROL BITS D7 TO D0 GAI15 0 0 0 1 GAI14 0 1 1 1 GAI13 0 0 0 1 GAI12 0 0 0 1 GAI11 0 0 0 1 GAI10 0 0 1 1 SUBADDRESS 05H Table 42 Analog input control 4 (AICO4); static gain control channel 2; 03H[1] and 05H[7:0] DECIMAL VALUE 0... ...144 145... ...511 GAIN (dB) -3 0 0 +6 SIGN BIT 03H[1] GAI28 0 0 0 1 GAI27 0 1 1 1 GAI26 0 0 0 1 CONTROL BITS D7 TO D0 GAI25 0 0 0 1 GAI24 0 1 1 1 GAI23 0 0 0 1 GAI22 0 0 0 1 GAI21 0 0 0 1 GAI20 0 0 1 1 2000 Mar 15 92 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.7 SUBADDRESS 06H SAA7114H Table 43 Horizontal sync start; 06H[7:0] DELAY TIME (STEP SIZE = 8/LLC) -128...-109 (50 Hz) -128...-108 (60 Hz) -108 (50 Hz)... -107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) 15.2.8 SUBADDRESS 07H 1 1 0 0 0 0 1 1 CONTROL BITS D7 TO D0 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 forbidden (outside available central counter range) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 1 forbidden (outside available central counter range) Table 44 Horizontal sync stop; 07H[7:0] DELAY TIME (STEP SIZE = 8/LLC) -128...-109 (50 Hz) -128...-108 (60 Hz) -108 (50 Hz)... -107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) 1 1 0 0 0 0 1 1 CONTROL BITS D7 TO D0 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 forbidden (outside available central counter range) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 1 forbidden (outside available central counter range) 2000 Mar 15 93 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.9 SUBADDRESS 08H SAA7114H Table 45 Sync control; 08H[7:0] BIT D7 D6 D5 DESCRIPTION automatic field detection field selection forced ODD/EVEN toggle SYMBOL VALUE AUFD FSEL FOET 0 1 0 1 0 1 D[4:3] horizontal time constant selection HTC[1:0] 00 01 10 11 D2 horizontal PLL HPLL VNOI[1:0] 0 1 D[1:0] vertical noise reduction 00 01 10 11 PLL closed PLL open; horizontal frequency fixed normal mode; recommended setting fast mode, applicable for stable sources only; automatic field detection (AUFD) must be disabled free running mode vertical noise reduction bypassed FUNCTION field state directly controlled via FSEL automatic field detection; recommended setting 50 Hz, 625 lines 60 Hz, 525 lines ODD/EVEN signal toggles only with interlaced source ODD/EVEN signal toggles fieldwise even if source is non-interlaced TV mode, recommended for poor quality TV signals only; do not use for new applications VTR mode, recommended if a deflection control circuit is directly connected to the SAA7114H reserved fast locking mode; recommended setting 2000 Mar 15 94 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.10 SUBADDRESS 09H Table 46 Luminance control; 09H[7:0] BIT D7 DESCRIPTION chrominance trap/comb filter bypass SYMBOL VALUE BYPS 0 1 D6 D5 adaptive luminance comb filter processing delay in non comb filter mode remodulation bandwidth for luminance; see Figs 12 to 15 YCOMB LDEL 0 1 0 1 LUBW 0 1 D[3:0] sharpness control, luminance filter characteristic; see Fig.16 LUFI[3:0] 0001 0010 0011 0100 0101 0110 0111 0000 1000 1001 1010 1011 1100 1101 1110 1111 15.2.11 SUBADDRESS 0AH Table 47 Luminance brightness control: decoder part; 0AH[7:0] CONTROL BITS D7 TO D0 OFFSET DBRI7 255 (bright) 128 (ITU level) 0 (dark) 1 1 0 DBRI6 1 0 0 DBRI5 1 0 0 DBRI4 1 0 0 DBRI3 1 0 0 DBRI2 1 0 0 FUNCTION SAA7114H chrominance trap or luminance comb filter active; default for CVBS mode chrominance trap or luminance comb filter bypassed; default for S-video mode disabled (= chrominance trap enabled, if BYPS = 0) active, if BYPS = 0 processing delay is equal to internal pipelining delay one (NTSC standards) or two (PAL standards) video lines additional processing delay small remodulation bandwidth (narrow chroma notch higher luminance bandwidth) large remodulation bandwidth (wider chroma notch smaller luminance bandwidth) resolution enhancement filter 8.0 dB at 4.1 MHz resolution enhancement filter 6.8 dB at 4.1 MHz resolution enhancement filter 5.1 dB at 4.1 MHz resolution enhancement filter 4.1 dB at 4.1 MHz resolution enhancement filter 3.0 dB at 4.1 MHz resolution enhancement filter 2.3 dB at 4.1 MHz resolution enhancement filter 1.6 dB at 4.1 MHz plain low-pass filter 2 dB at 4.1 MHz low-pass filter 3 dB at 4.1 MHz low-pass filter 3 dB at 3.3 MHz; 4 dB at 4.1 MHz low-pass filter 3 dB at 2.6 MHz; 8 dB at 4.1 MHz low-pass filter 3 dB at 2.4 MHz; 14 dB at 4.1 MHz low-pass filter 3 dB at 2.2 MHz; notch at 3.4 MHz low-pass filter 3 dB at 1.9 MHz; notch at 3.0 MHz low-pass filter 3 dB at 1.7 MHz; notch at 2.5 MHz D4 DBRI1 1 0 0 DBRI0 1 0 0 2000 Mar 15 95 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.12 SUBADDRESS 0BH Table 48 Luminance contrast control; decoder part; 0BH[7:0] CONTROL BITS D7 TO D0 GAIN DCON7 1.984 (maximum) 1.063 (ITU level) 1.0 0 (luminance off) -1 (inverse luminance) -2 (inverse luminance) 15.2.13 SUBADDRESS 0CH Table 49 Chrominance saturation control: decoder part; 0CH[7:0] CONTROL BITS D7 TO D0 GAIN DSAT7 1.984 (maximum) 1.0 (ITU level) 0 (colour off) -1 (inverse chrominance) -2 (inverse chrominance) 15.2.14 SUBADDRESS 0DH Table 50 Chrominance hue control; 0DH[7:0] CONTROL BITS D7 TO D0 HUE PHASE (DEG) HUEC7 +178.6... ...0... ...-180 0 0 1 HUEC6 1 0 0 HUEC5 1 0 0 HUEC4 1 0 0 HUEC3 1 0 0 HUEC2 1 0 0 0 0 0 1 1 DSAT6 1 1 0 1 0 DSAT5 1 0 0 0 0 DSAT4 1 0 0 0 0 DSAT3 1 0 0 0 0 DSAT2 1 0 0 0 0 0 0 0 0 1 1 DCON6 1 1 1 0 1 0 DCON5 1 0 0 0 0 0 DCON4 1 0 0 0 0 0 DCON3 1 0 0 0 0 0 DCON2 1 1 0 0 0 0 SAA7114H DCON1 1 0 0 0 0 0 DCON0 1 0 0 0 0 0 DSAT1 1 0 0 0 0 DSAT0 1 0 0 0 0 HUEC1 1 0 0 HUEC0 1 0 0 2000 Mar 15 96 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.15 SUBADDRESS 0EH Table 51 Chrominance control 1; 0EH[7:0] FUNCTION BIT D7 DESCRIPTION clear DTO SYMBOL CSTDO VALUE 50 Hz/625 LINES 0 1 disabled SAA7114H 60 Hz/525 LINES Every time CDTO is set, the internal subcarrier DTO phase is reset to 0 and the RTCO output generates a logic 0 at time slot 68 (see external document "RTC Functional Description", available on request). So an identical subcarrier phase can be generated by an external device (e.g. an encoder). PAL BGDHI (4.43 MHz) NTSC 4.43 (50 Hz) Combination-PAL N (3.58 MHz) NTSC N (3.58 MHz) reserved SECAM NTSC M (3.58 MHz) PAL 4.43 (60 Hz) NTSC 4.43 (60 Hz) PAL M (3.58 MHz) NTSC-Japan (3.58 MHz) reserved reserved; do not use reserved; do not use chrominance vertical filter and PAL phase error correction on (during active video lines) chrominance vertical filter and PAL phase error correction permanently off nominal time constant fast time constant for special applications disabled active D[6:4] colour standard selection CSTD[2:0] 000 001 010 011 100 101 110 111 D3 disable chrominance vertical filter and PAL phase error correction fast colour time constant adaptive chrominance comb filter DCVF 0 1 D2 D0 FCTC CCOMB 0 1 0 1 15.2.16 SUBADDRESS 0FH Table 52 Chrominance gain control; 0FH[7:0] BIT D7 DESCRIPTION automatic chrominance gain control SYMBOL ACGC VALUE 0 1 on programmable gain via CGAIN6 to CGAIN0; need to be set for SECAM standard FUNCTION D[6:0] chrominance gain value (if ACGC is set to logic 1) CGAIN[6:0] 000 0000 minimum gain (0.5) 010 0100 nominal gain (1.125) 111 1111 maximum gain (7.5) 2000 Mar 15 97 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.17 SUBADDRESS 10H Table 53 Chrominance control 2; 10H[7:0] BIT DESCRIPTION SYMBOL OFFU[1:0] VALUE 00 01 01 11 D[5:4] fine offset adjustment R-Y component OFFV[1:0] 00 01 10 11 D3 chrominance bandwidth; see Figs 10 and 11 CHBW LCBW[2:0] 0 1 D[2:0] combined luminance/chrominance bandwidth adjustment; see Figs 10 to 16 000 0 LSB 1 1 3 1 1 3 4 2 4 SAA7114H FUNCTION LSB LSB LSB D[7:6] fine offset adjustment B-Y component 0 LSB 4LSB 2LSB 4LSB small wide smallest chrominance bandwidth/largest luminance bandwidth ... to ... largest chrominance bandwidth/smallest luminance bandwidth ... 111 15.2.18 SUBADDRESS 11H Table 54 Mode/delay control; 11H[7:0] BIT D7 D6 colour on polarity of RTS1 output signal DESCRIPTION SYMBOL COLO RTP1 HDEL[1:0] VALUE 0 1 0 1 D[5:4] fine position of HS (steps in 2/LLC) 00 01 10 11 D3 polarity of RTS0 output signal RTP0 YDEL[2:0] 0 1 D[2:0] luminance delay compensation (steps in 2/LLC) 100 000 011 FUNCTION automatic colour killer enabled colour forced on non inverted inverted 0 1 2 3 non inverted inverted -4... ...0... ...3 2000 Mar 15 98 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.19 SUBADDRESS 12H Table 55 RT signal control: RTS0 output; 12H[3:0] The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]]. RTS0 OUTPUT 3-state Constant LOW CREF (13.5 MHz toggling pulse; see Fig.23) CREF2 (6.75 MHz toggling pulse; see Fig.23) HL; horizontal lock indicator (note 1): HL = 0: unlocked HL = 1: locked VL; vertical and horizontal lock: VL = 0: unlocked VL = 1: locked DL, vertical and horizontal lock and colour detected: DL = 0: unlocked DL = 1: locked Reserved HREF, horizontal reference signal; indicates 720 pixels valid data on the expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval (see Fig.23). HS: programmable width in LLC8 steps via HSB[7:0]06H[7:0] and HSS[7:0]07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0]11H[5:4] (see Fig.23) HQ; HREF gated with VGATE Reserved V123; vertical sync (see vertical timing diagrams Figs 21 and 22) VGATE; programmable via VSTA[8:0]17H[0]15H[7:0], VSTO[8:0]17H[1]16H[7:0] and VGPS[17H[2]] LSBs of the 9-bit ADC's FID; position programmable via STA[8:0]17H[0]15H[7:0]; see vertical timing diagrams Figs 21 and 22 Note 1. Function of HL is selectable via HLSEL[13H[3]]: a) HLSEL = 0: HL is standard horizontal lock indicator. 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 0 0 1 0 1 SAA7114H RTSE03 RTSE02 RTSE01 RTSE00 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. VCRs). 2000 Mar 15 99 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 56 RT signal control: RTS1 output; 12H[7:4] The polarity of any signal on RTS1 can be inverted via RTP1[11H[6]]. RTS1 OUTPUT 3-state Constant LOW CREF (13.5 MHz toggling pulse; see Fig.23) CREF2 (6.75 MHz toggling pulse; see Fig.23) HL; horizontal lock indicator (note 1): HL = 0: unlocked HL = 1: locked VL; vertical and horizontal lock: VL = 0: unlocked VL = 1: locked DL, vertical and horizontal lock and colour detected: DL = 0: unlocked DL = 1: locked Reserved HREF, horizontal reference signal; indicates 720 pixels valid data on the expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval (see Fig.23). HS: programmable width in LLC8 steps via HSB[7:0]06H[7:0] and HSS[7:0]07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0]11H[5:4] (see Fig.23) HQ; HREF gated with VGATE Reserved V123; vertical sync (see vertical timing diagrams Figs 21 and 22) VGATE; programmable via VSTA[8:0]17H[0]15H[7:0], VSTO[8:0]17H[1]16H[7:0] and VGPS[17H[2]] LSBs of the 9-bit ADC's FID; position programmable via STA[8:0]17H[0]15H[7:0]; see vertical timing diagrams Figs 21 and 22 Note 1. Function of HL is selectable via HLSEL[13H[3]]: a) HLSEL = 0: HL is standard horizontal lock indicator. 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 0 0 1 0 1 SAA7114H RTSE13 RTSE12 RTSE11 RTSE10 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. VCRs). 2000 Mar 15 100 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.20 SUBADDRESS 13H Table 57 RT/X-port output control; 13H[7:0] BIT D7 D6 DESCRIPTION RTCO output enable X-port XRH output selection SYMBOL VALUE RTCE XRHS 0 1 0 1 3-state enabled HREF (see Fig.23) HS: FUNCTION SAA7114H programmable width in LLC8 steps via HSB[7:0]06H[7:0] and HSS[7:0]07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0]11H[5:4] (see Fig.23) D[5:4] X-port XRV output selection XRVS[1:0] 00 01 10 11 D3 horizontal lock indicator selection HLSEL OFTS[2:0] 0 1 000 001 V123 (see Figs 21 and 22) ITU 656 related field ID (see Figs 21 and 22) inverted V123 inverted ITU 656 related field ID copy of inverted HLCK status bit (default) fast horizontal lock indicator (for special applications only) ITU 656 ITU 656 like format with modified field blanking according to VGATE position (programmable via VSTA8 to VSTA0, VSTO8 to VSTO0 and VGPS, subaddresses 15H, 16H and 17H) YUV 4 : 2 : 2 8-bit format (no SAV/EAV codes inserted) reserved multiplexed AD2/AD1 bypass (bits 8 to 1) dependent on mode settings; if both ADCs are selected AD2 is output at CREF = 1 and AD1 is output at CREF = 0 multiplexed AD2/AD1 bypass (bits 7 to 0) dependent on mode settings; if both ADCs are selected AD2 is output at CREF = 1 and AD1 is output at CREF = 0 reserved multiplexed ADC MSB/LSB bypass dependent on mode settings; only one ADC should be selected at a time; ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0 are outputs at CREF = 0 D[2:0] XPD7 to XPD0 (port output format selection); see Section 9.4 010 011 100 101 110 111 2000 Mar 15 101 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.21 SUBADDRESS 14H Table 58 Analog/ADC/compatibility control; 14H[7:0] BIT D7 DESCRIPTION compatibility bit for SAA7199 update time interval for AGC value SYMBOL CM99 VALUE 0 1 UPTCV AOSL[1:0] 0 1 00 01 10 11 D3 D2 XTOUT output enable decoder status byte selection; see Table 64 XTOUTE OLDSB APCK[1:0] 0 1 0 1 00 01 10 11 off (default) FUNCTION SAA7114H on (to be set only if SAA7199 is used for re-encoding in conjunction with RTCO active) horizontal update (once per line) vertical update (once per field) AOUT connected to internal test point 1 AOUT connected to input AD1 AOUT connected to input AD2 AOUT connected to internal test point 2 pin 4 (XTOUT) 3-stated pin 4 (XTOUT) enabled standard backward compatibility to SAA7112 application dependent D6 D[5:4] analog test select D[1:0] ADC sample clock phase delay 2000 Mar 15 102 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 59 VGATE pulse; FID polarity change; 17H[0] and 15H[7:0] Start of VGATE pulse (LOW-to-HIGH transition) and polarity change of FID pulse, VGPS = 0; see Figs 21 and 22. FRAME LINE COUNTING 1st 2nd 1st 2nd 1st 2nd 60 Hz 1st 2nd 1st 2nd 1st 2nd 103 1 314 2 315 312 625 4 267 5 268 265 3 DECIMAL VALUE MSB 17H[0] VSTA8 50 Hz 312 0... ...310 262 0... ...260 1 0 1 1 0 1 VSTA7 0 0 0 0 0 0 VSTA6 0 0 0 0 0 0 CONTROL BITS D7 TO D0 VSTA5 1 0 1 0 0 0 VSTA4 1 0 1 0 0 0 VSTA3 1 0 0 0 0 0 VSTA2 0 0 1 1 0 1 VSTA1 0 0 1 1 0 0 VSTA0 0 0 1 0 0 1 2000 Mar 15 15.2.22 SUBADDRESS 15H Philips Semiconductors PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler FIELD Preliminary specification SAA7114H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 60 VGATE stop; 17H[1] and 16H[7:0] Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Figs 21 and 22. FRAME LINE COUNTING 1st 2nd 1st 2nd 1st 2nd 60 Hz 1st 2nd 1st 2nd 1st 2nd 104 1 314 2 315 312 625 4 267 5 268 265 3 ...260 1 0 0 0 0 0 1 0 1 0... 0 0 0 0 0 0 0 0 0 262 1 0 0 0 0 0 1 1 0 ...310 1 0 0 1 1 0 1 1 1 0... 0 0 0 0 0 0 0 0 0 DECIMAL VALUE 312 MSB 17H[1] VSTO8 50 Hz 1 VSTO7 0 VSTO6 0 CONTROL BITS D7 TO D0 VSTO5 1 VSTO4 1 VSTO3 1 VSTO2 0 VSTO1 0 VSTO0 0 2000 Mar 15 15.2.23 SUBADDRESS 16H Philips Semiconductors PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler FIELD Preliminary specification SAA7114H Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.24 SUBADDRESS 17H Table 61 Miscellaneous/VGATE MSBs; 17H[7:6] and 17H[2:0] BIT D7 D6 D2 D1 D0 DESCRIPTION LLC output enable LLC2 output enable alternative VGATE position MSB VGATE stop MSB VGATE start SYMBOL VALUE LLCE LLC2E VGPS VSTO8 VSTA8 0 1 0 1 0 1 enable 3-state enable 3-state FUNCTION SAA7114H VGATE position according to Tables 59 and 60 VGATE occurs one line earlier during field 2 see Table 60 see Table 59 15.2.25 SUBADDRESS 18H Table 62 Raw data gain control; RAWG[7:0]18H[7:0] See Fig.18. CONTROL BITS D7 TO D0 GAIN RAWG7 255 (double amplitude) 128 (nominal level) 0 (off) 15.2.26 SUBADDRESS 19H Table 63 Raw data offset control; RAWO[7:0]19H[7:0] See Fig.18. CONTROL BITS D7 TO D0 OFFSET RAWO7 -128 LSB 0 LSB +128 LSB 0 1 1 RAWO6 0 0 1 RAWO5 0 0 1 RAWO4 0 0 1 RAWO3 0 0 1 RAWO2 0 0 1 RAWO1 0 0 1 RAWO0 0 0 1 0 0 0 RAWG6 1 1 0 RAWG5 1 0 0 RAWG4 1 0 0 RAWG3 1 0 0 RAWG2 1 0 0 RAWG1 1 0 0 RAWG0 1 0 0 2000 Mar 15 105 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.2.27 SUBADDRESS 1FH (READ ONLY REGISTER) Table 64 Status byte video decoder; 1FH[7:0] BIT D7 D6 DESCRIPTION status bit for interlace detection status bit for horizontal and vertical loop status bit for locked horizontal frequency D5 D4 D3 D2 D1 identification bit for detected field frequency gain value for active luminance channel is limited; maximum (top) gain value for active luminance channel is limited; minimum (bottom) white peak loop is activated copy protected source detected according to macrovision version up to 7.01 slow time constant active in WIPA mode D0 ready for capture (all internal loops locked) colour signal in accordance with selected standard has been detected 15.3 Programming register audio clock generation I2C-BUS OLDSB CONTROL VALUE 14H[2] BIT INTL HLVLN HLCK FIDT GLIMT GLIMB WIPA COPRO SLTCA RDCAP CODE - 0 1 - - - - 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAA7114H FUNCTION non-interlaced interlaced both loops locked unlocked locked unlocked 50 Hz 60 Hz not active active not active active not active active not active active not active active not active active not active active See equations in Section 8.6 and examples in Tables 21 and 22. 15.3.1 SUBADDRESSES 30H TO 32H Table 65 Audio master clock (AMCLK) cycles per field SUBADDRESS 30H 31H 32H ACPF7 ACPF15 - ACPF6 ACPF14 - ACPF5 ACPF13 - CONTROL BITS D7 TO D0 ACPF4 ACPF12 - ACPF3 ACPF11 - ACPF2 ACPF10 - ACPF1 ACPF9 ACPF17 ACPF0 ACPF8 ACPF16 2000 Mar 15 106 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.3.2 SUBADDRESSES 34H TO 36H SAA7114H Table 66 Audio master clock (AMCLK) nominal increment SUBADDRESS 34H 35H 36H 15.3.3 ACNI7 ACNI15 - ACNI6 ACNI14 - ACNI5 ACNI13 ACNI21 CONTROL BITS D7 TO D0 ACNI4 ACNI12 ACNI20 ACNI3 ACNI11 ACNI19 ACNI2 ACNI10 ACNI18 ACNI1 ACNI9 ACNI17 ACNI0 ACNI8 ACNI16 SUBADDRESS 38H Table 67 Clock ratio AMCLK (audio master clock) to ASCLK (serial bit clock) SUBADDRESS 38H 15.3.4 - - SDIV5 CONTROL BITS D7 TO D0 SDIV4 SDIV3 SDIV2 SDIV1 SDIV0 SUBADDRESS 39H Table 68 Clock ratio ASCLK (serial bit clock) to ALRCLK (channel select clock) SUBADDRESS 39H 15.3.5 - - LRDIV5 CONTROL BITS D7 TO D0 LRDIV4 LRDIV3 LRDIV2 LRDIV1 LRDIV0 SUBADDRESS 3AH Table 69 Audio clock control; 3AH[3:0] BIT D3 D2 D1 D0 DESCRIPTION audio PLL modes audio master clock vertical reference ALRCLK phase ASCLK phase SYMBOL VALUE APLL AMVR LRPH SCPH 0 1 0 1 0 1 0 1 15.4 15.4.1 Programming register VBI-data slicer SUBADDRESS 40H FUNCTION PLL active, AMCLK is field-locked PLL open, AMCLK is free-running vertical reference pulse is taken from internal decoder vertical reference is taken from XRV input (expansion port) ALRCLK edges triggered by falling edges of ASCLK ALRCLK edges triggered by rising edges of ASCLK ASCLK edges triggered by falling edges of AMCLK ASCLK edges triggered by rising edges of AMCLK Table 70 Slicer control 1; 40H[6:4] BIT D6 DESCRIPTION Hamming check SYMBOL VALUE HAM_N 0 1 D5 D4 framing code error amplitude searching FCE HUNT_N 0 1 0 1 FUNCTION Hamming check for 2 bytes after framing code, dependent on data type (default) no Hamming check one framing code error allowed no framing code errors allowed amplitude searching active (default) amplitude searching stopped 2000 Mar 15 107 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.4.2 SUBADDRESSES 41H TO 57H SAA7114H Table 71 Line control register; LCR2 to LCR24 (41H to 57H) See Sections 8.2 and 8.4. D[7:4] (41H TO 57H) NAME DESCRIPTION FRAMING CODE DT[3:0]62H[3:0] (FIELD 1) WST625 CC625 VPS WSS WST525 CC525 Test line Intercast VITC625 Reserved NABTS Japtext JFS teletext EuroWST, CCST European closed caption video programming service wide screen signalling bits US teletext (WST) US closed caption (line 21) video component signal, VBI region raw data VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) 27H 001 9951H 1E3C1FH 27H 001 - - programmable programmable programmable - - programmable (A7H) programmable - 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DT[3:0]62H[3:0] (FIELD 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D[3:0] (41H TO 57H) General text teletext Active video video component signal, active video region (default) 15.4.3 SUBADDRESS 58H Table 72 Programmable framing code; slicer set 58H[7:0] According to Tables 14 and 71. FRAMING CODE FOR PROGRAMMABLE DATA TYPES Default value 15.4.4 SUBADDRESS 59H CONTROL BITS D7 TO D0 FC[7:0] = 40H Table 73 Horizontal offset for slicer; slicer set 59H and 5BH HORIZONTAL OFFSET Recommended value CONTROL BITS D[2:0]5BH[2:0] HOFF[10:8] = 3H CONTROL BITS D[7:0]59H[7:0] HOFF[7:0] = 47H 2000 Mar 15 108 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.4.5 SUBADDRESS 5AH SAA7114H Table 74 Vertical offset for slicer; slicer set 5AH and 5BH CONTROL BIT D[4]5BH[4] VERTICAL OFFSET VOFF8 Minimum value 0 Maximum value 312 Value for 50 Hz 625 lines input Value for 60 Hz 525 lines input 15.4.6 SUBADDRESS 5BH 0 1 0 0 VOFF[7:0] 00H 38H 03H 06H CONTROL BITS D[7:0]5AH[7:0] Table 75 Field offset, and MSBs for horizontal and vertical offsets; slicer set 5BH[7:6] See Sections 15.4.4 and 15.4.5 for HOFF[10:8]5BH[2:0] and VOFF8[5BH[4]]. BIT D7 DESCRIPTION SYMBOL VALUE field offset FOFF 0 1 D6 recode RECODE 0 1 15.4.7 SUBADDRESS 5DH FUNCTION no modification of internal field indicator (default for 50 Hz 625 lines input sources) invert field indicator (default for 60 Hz 525 lines input sources) let data unchanged (default) convert 00H and FFH data bytes into 03H and FCH Table 76 Header and data identification (DID; ITU 656) code control; slicer set 5DH[7:0] BIT D7 DESCRIPTION field ID and V-blank selection for text output (F and V reference selection) SYMBOL FVREF VALUE 0 1 DID[5:0] FUNCTION F and V output of slicer is LCR table dependent F and V output is taken from decoder real time signals EVEN_CCIR and VBLNK_CCIR D[5:0] default; DID[5:0] = 00H special cases of DID programming 15.4.8 SUBADDRESS 5EH 00 0000 ANC header framing; see Fig.30 and Table 20 11 1110 DID[5:0] = 3EH SAV/EAV framing, with FVREF = 1 11 1111 DID[5:0] = 3FH SAV/EAV framing, with FVREF = 0 Table 77 Sliced data identification (SDID) code; slicer set 5EH[5:0] BIT DESCRIPTION SYMBOL VALUE SDID[5:0] 00H default FUNCTION D[5:0] SDID codes 2000 Mar 15 109 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.4.9 SUBADDRESS 60H (READ-ONLY REGISTER) SAA7114H Table 78 Slicer status byte 0; 60H[6:2] BIT D6 D5 D4 D3 D2 DESCRIPTION framing code valid framing code valid VPS valid PALplus valid close caption valid SYMBOL VALUE FC8V FC7V VPSV PPV CCV 0 1 0 1 0 1 0 1 0 1 FUNCTION no framing code (0 error) in the last frame detected framing code with 0 error detected no framing code (1 error) in the last frame detected framing code with 1 error detected no VPS in the last frame VPS detected no PALplus in the last frame PALplus detected no closed caption in the last frame closed caption detected 15.4.10 SUBADDRESSES 61H AND 62H (READ-ONLY REGISTERS) Table 79 Slicer status byte 1; 61H[5:0] and slicer status byte 2; 62H[7:0] SUBADDRESS 61H 62H BIT D5 D[4:0] D[7:4] D[3:0] 15.5 15.5.1 SYMBOL F21_N LN[8:4] LN[3:0] DT[3:0] data type; according to Table 14 line number DESCRIPTION field ID as seen by the VBI slicer; for field 1: D5 = 0 Programming register interfaces and scaler part SUBADDRESS 80H Table 80 Global control 1; global set 80H[3:0] X = don't care. CONTROL BITS D3 TO D0 I-PORT AND SCALER BACK-END CLOCK SELECTION ICKS3 ICLK output and back-end clock is line-locked clock LLC from decoder ICLK output and back-end clock is XCLK from X-port ICLK output is LLC and back-end clock is LLC2 clock Back-end clock is the ICLK input IDQ pin carries the data qualifier IDQ pin carries a gated back-end clock (IDQ AND CLK) IDQ generation only for valid data IDQ qualifies valid data inside the scaling region and all data outside the scaling region Note 1. Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1. X X X X X X 0 1 ICKS2 X X X(1) X 0 1 X X ICKS1 0 0 1 1 X X X X ICKS0 0 1 0 1 X X X X 2000 Mar 15 110 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 81 Global control 1; global set 80H[6:4] SWRST moved to subaddress 88H[5]; X = don't care. SAA7114H CONTROL BITS D6 TO D4 TASK ENABLE CONTROL SMOD Task of register set A is disabled Task of register set A is enabled Task of register set B is disabled Task of register set B is enabled The scaler window defines the F and V timing of the scaler output VBI-data slicer defines the F and V timing of the scaler output 15.5.2 SUBADDRESSES 83H TO 87H X X X X 0 1 TEB X X 0 1 X X TEA 0 1 X X X X Table 82 X-port I/O enable and output clock phase control; global set 83H[5:4] CONTROL BITS D5 AND D4 OUTPUT CLOCK PHASE CONTROL XPCK1 XCLK default output phase, recommended value XCLK output inverted XCLK phase shifted by about 3 ns XCLK output inverted and shifted by about 3 ns Table 83 X-port I/O enable and output clock phase control; global set 83H[2:0] X = don't care. CONTROL BITS D2 TO D0 X-PORT I/O ENABLE XRQT X-port output is disabled by software X-port output is enabled by software X-port output is enabled by pin XTRI at logic 0 X-port output is enabled by pin XTRI at logic 1 XRDY output signal is A/B task flag from event handler (A = 1) XRDY output signal is ready signal from scaler path (XRDY = 1 means SAA7114H is ready to receive data) X X X X 0 1 XPE1 0 0 1 1 X X XPE0 0 1 0 1 X X 0 0 1 1 XPCK0 0 1 0 1 2000 Mar 15 111 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 84 I-port output signal definitions; global set 84H[3:0] X = don't care. SAA7114H CONTROL BITS D3 TO D0 I-PORT OUTPUT SIGNAL DEFINITIONS IDV1 IGPH is a H-gate signal, framing the scaler output IGPH is an extended H-gate (framing H-gate during scaler output and scaler input H-reference outside the scaler window) IGPH is a horizontal trigger pulse, on active going edge of H-gate IGPH is a horizontal trigger pulse, on active going edge of extended H-gate IGPV is a V-gate signal, framing scaled output lines IGPV is the reference signal from scaler input IGPV is a vertical trigger pulse, derived from V-gate IGPV is a vertical trigger pulse derived from input V-reference Table 85 I-port signal definitions; global set 84H[5:4] and 86H[4] CONTROL BITS I-PORT SIGNAL DEFINITIONS 86H[4] IDG12 IGP1 is output field ID, as defined by OFIDC[90H[6]] IGP1 is A/B task flag, as defined by CONLH[90H[7]] IGP1 is sliced data flag, framing the sliced VBI-data at the I-port IGP1 is set to logic 0 (default polarity) IGP1 is the output FIFO almost filled flag IGP1 is the output FIFO overflow flag IGP1 is the output FIFO almost full flag, level to be programmed in subaddress 86H IGP1 is the output FIFO almost empty flag, level to be programmed in subaddress 86H 0 0 0 0 1 1 1 1 84H[5:4] IDG11 0 0 1 1 0 0 1 1 IDG10 0 1 0 1 0 1 0 1 X X X X 0 0 1 1 IDV0 X X X X 0 1 0 1 IDH1 0 0 1 1 X X X X IDH0 0 1 0 1 X X X X 2000 Mar 15 112 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 86 I-port signal definitions; global set 84H[7:6] and 86H[5] SAA7114H CONTROL BITS I-PORT SIGNAL DEFINITIONS 86H[5] IDG02 IGP0 is output field ID, as defined by OFIDC[90H[6]] IGP0 is A/B task flag, as defined by CONLH[90H[7]] IGP0 is sliced data flag, framing the sliced VBI-data at the I-port IGP0 is set to logic 0 (default polarity) IGP0 is the output FIFO almost filled flag IGP0 is the output FIFO overflow flag IGP0 is the output FIFO almost full flag, level to be programmed in subaddress 86H IGP0 is the output FIFO almost empty flag, level to be programmed in subaddress 86H Table 87 I-port reference signal polarities; global set 85H[4:0] X = don't care. CONTROL BITS D4 TO D0 I-PORT REFERENCE SIGNAL POLARITIES IGP0P IDQ at default polarity (1 = active) IDQ is inverted IGPH at default polarity (1 = active) IGPH is inverted IGPV at default polarity (1 = active) IGPV is inverted IGP1 at default polarity IGP1 is inverted IGP0 at default polarity IGP0 is inverted Table 88 X-port signal definitions text slicer; global set 85H[7:5] X = don't care. CONTROL BITS D7 TO D5 X-PORT SIGNAL DEFINITIONS TEXT SLICER ISWP1 Video data limited to range 1 to 254 Video data limited to range 8 to 247 Dword byte swap, influences serial output timing D0 D1 D2 D3 FF 00 00 SAV CB0 Y0 CR0 Y1 D1 D0 D3 D2 00 FF SAV 00 Y0 CB0 Y1 CR0 D2 D3 D0 D1 00 SAV FF 00 CR0 Y1 CB0 Y0 D3 D2 D1 D0 SAV 00 00 FF Y1 CR0 Y0 CB0 X X 0 0 1 1 ISWP0 X X 0 1 0 1 ILLV 0 1 X X X X X X X X X X X X 0 1 IGP1P X X X X X X 0 1 X X IGVP X X X X 0 1 X X X X IGHP X X 0 1 X X X X X X IDQP 0 1 X X X X X X X X 0 0 0 0 1 1 1 1 84H[7:6] IDG01 0 0 1 1 0 0 1 1 IDG00 0 1 0 1 0 1 0 1 2000 Mar 15 113 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 89 I-port FIFO flag control and arbitration; global set 86H[3:0] X = don't care. SAA7114H CONTROL BITS D3 TO D0 I-PORT FIFO FLAG CONTROL AND ARBITRATION FFL1 FAE FIFO flag almost empty level <16 Dwords <8 Dwords <4 Dwords 0 Dwords FAF FIFO flag almost full level 16 Dwords 24 Dwords 28 Dwords 32 Dwords Table 90 I-port FIFO flag control and arbitration; global set 86H[7:4] X = don't care. CONTROL BITS D7 TO D4 FUNCTION VITX1 See subaddress 84H: IDG11 and IDG10 See subaddress 84H: IDG01 and IDG00 I-port signal definitions I-port data output inhibited Only video data are transferred Only text data are transferred (no EAV, SAV will occur) Text and video data are transferred, text has priority 0 0 1 1 0 1 0 1 X X X X X X X X X X X X VITX0 X X X X IDG02 X X 0 1 IDG12 0 1 X X 0 0 1 1 0 1 0 1 X X X X X X X X X X X X X X X X 0 0 1 1 0 1 0 1 FFL0 FEL1 FEL0 2000 Mar 15 114 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 91 I-port I/O enable, output clock and gated clock phase control; global set 87H[7:4] SAA7114H CONTROL BITS D7 TO D4(1) OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL ICLK default output phase ICLK phase shifted by 12 clock cycle recommended for ICKS1 = 1 and ICKS0 = 0 (subaddress 80H) ICLK phase shifted by about 3 ns ICLK phase shifted by 1 2 IPCK3(2) IPCK2(2) IPCK1 IPCK0 X X X X 0 0 1 1 X X X X 0 1 0 1 0 0 1 1 X X X X 0 1 0 1 X X X X clock cycle + about 3 ns alternatively to setting `01' IDQ = gated clock default output phase IDQ = gated clock phase shifted by 12 clock cycle recommended for gated clock output IDQ = gated clock phase shifted by about 3 ns IDQ = gated clock phase shifted by 12 clock cycle + about 3 ns alternatively to setting `01' Notes 1. X = don't care. 2. IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1). Table 92 I-port I/O enable, output clock and gated clock phase control; global set 87H[1:0] CONTROL BITS D1 AND D0 I-PORT I/O ENABLE IPE1 I-port output is disabled by software I-port output is enabled by software I-port output is enabled by pin ITRI at logic 0 I-port output is enabled by pin ITRI at logic 1 15.5.3 SUBADDRESS 88H 0 0 1 1 IPE0 0 1 0 1 Table 93 Power save control; global set 88H[3] and 88H[1:0] X = don't care. CONTROL BITS POWER SAVE CONTROL 88H[3] SLM3 Decoder and VBI slicer are in operational mode Decoder and VBI slicer are in power-down mode; scaler only operates, if scaler input and ICLK source is the X-port (refer to subaddresses 80H and 91H/C1H) Scaler is in operational mode Scaler is in power-down mode; scaler in power-down stops I-port output Audio clock generation active Audio clock generation in power-down and output disabled X X X X 0 1 88H[1:0] SLM1 X X 0 1 X X SLM0 0 1 X X X X 2000 Mar 15 115 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 94 Power save control; global set 88H[7:4] SAA7114H CONTROL BITS D7 TO D4(1) POWER SAVE CONTROL CH4EN DPROG = 0 after reset DPROG = 1 can be used to assign that the device has been programmed; this bit can be monitored in the scalers status byte, bit PRDON; if DPROG was set to logic 1 and PRDON status bit shows a logic 0 a power- or start-up fail has occurred Scaler path is reset to it's idle state, software reset Scaler is switched back to operation AD1x analog channel is in power-down mode AD1x analog channel is active AD2x analog channel is in power-down mode AD2x analog channel is active Notes 1. X = don't care. 2. Bit SWRST is now located here. 15.5.4 SUBADDRESS 8FH (READ-ONLY REGISTER) X X CH2EN X X SWRST(2) X X DPROG 0 1 X X X X 0 1 X X 0 1 X X 0 1 X X X X X X X X X X Table 95 Status information scaler part; 8FH[7:0] BIT D7 D6 D5 D4 D3 D2 I2C-BUS STATUS BIT XTRI ITRI FFIL FFOV PRDON ERR_OF FUNCTION(1) status on input pin XTRI, if not used for 3-state control, usable as hardware flag for software use status on input pin ITRI, if not used for 3-state control, usable as hardware flag for software use status of the internal `FIFO almost filled' flag status of the internal `FIFO overflow' flag copy of bit DPROG, can be used to detect power-up and start-up fails error flag of scalers output formatter, normally set, if the output processing needs to be interrupted, due to input/output data rate conflicts, e.g. if output data rate is much too low and all internal FIFO capacity used status of the field sequence ID at the scalers input status of the field sequence ID at the scalers output, scaler processing dependent D1 D0 Note FIDSCI FIDSCO 1. Status information is unsynchronized and shows the actual status at the time of I2C-bus read. 2000 Mar 15 116 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.5.5 SUBADDRESSES 90H AND C0H SAA7114H Table 96 Task handling control; register set A (90H[2:0]) and B (C0H[2:0]) X = don't care. CONTROL BITS D2 TO D0 EVENT HANDLER CONTROL RPTSK Event handler triggers immediately after finishing a task Event handler triggers with next V-sync Event handler triggers with field ID = 0 Event handler triggers with field ID = 1 If active task is finished, handling is taken over by the next task Active task is repeated once, before handling is taken over by the next task Table 97 Task handling control; register set A (90H[5:3]) and B (C0H[5:3]) CONTROL BITS D5 TO D3 EVENT HANDLER CONTROL FSKP2 Active task is carried out directly 1 field is skipped before active task is carried out ... fields are skipped before active task is carried out 6 fields are skipped before active task is carried out 7 fields are skipped before active task is carried out Table 98 Task handling control; register set A (90H[7:6]) and B (C0H[7:6]) X = don't care. CONTROL BITS D7 AND D6 EVENT HANDLER CONTROL CONLH Output field ID is field ID from scaler input Output field ID is task status flag, which changes every time an selected task is activated (not synchronized to input field ID) Scaler SAV/EAV byte bit D7 and task flag = 1, default Scaler SAV/EAV byte bit D7 and task flag = 0 X X 0 1 OFIDC 0 1 X X 0 0 ... 1 1 FSKP1 0 0 ... 1 1 FSKP0 0 1 ... 0 1 X X X X 0 1 STRC1 0 0 1 1 X X STRC0 0 1 0 1 X X 2000 Mar 15 117 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.5.6 SUBADDRESSES 91H TO 93H SAA7114H Table 99 X-port formats and configuration; register set A (91H[2:0]) and B (C1H[2:0]) SCALER INPUT FORMAT AND CONFIGURATION FORMAT CONTROL Input is YUV 4 : 2 : 2 like sampling scheme Input is YUV 4 : 1 : 1 like sampling scheme Chroma is provided every line, default Chroma is provided every 2nd line Chroma is provided every 3rd line Chroma is provided every 4th line Notes 1. X = don't care. 2. FSC2 and FSC1 only to be used, if X-port input source don't provide chroma information for every input line. X-port input stream must contain dummy chroma bytes. Table 100 X-port formats and configuration; register set A (91H[7:3]) and B (C1H[7:3]) X = don't care. SCALER INPUT FORMAT AND CONFIGURATION SOURCE SELECTION Only if XRQT[83H[2]] = 1: scaler input source reacts on SAA7114H request Scaler input source is a continuous data stream, which cannot be interrupted (must be logic 1, if SAA7114H decoder part is source of scaler or XRQT[83H[2]] = 0) Scaler input source is data from decoder, data type is provided according to Table 14 Scaler input source is YUV data from X-port Scaler input source is raw digital CVBS from selected analog channel, for backward compatibility only, further use is not recommended Scaler input source is raw digital CVBS (or 16-bit Y + UV, if no 16-bit output are active) from X-port SAV/EAV code bits D6 and D5 (F and V) may change between SAV and EAV SAV/EAV code bits D6 and D5 (F and V) are synchronized to scalers output line start SAV/EAV code bit D5 (V) and V-gate on pin IGPV as generated by the internal processing, see Fig.36 SAV/EAV code bit D5 (V) and V-gate are inverted CONTROL BITS D7 TO D3 CONLV X X HLDFV X X SCSRC1 SCSRC0 X X X X SCRQE 0 1 CONTROL BITS D2 TO D0(1) FSC2(2) X X 0 0 1 1 FSC1(2) X X 0 1 0 1 FSC0 0 1 X X X X X X X X X X 0 0 1 0 1 0 X X X X X X 0 1 X 0 1 X X 1 X X X X 1 X X X X X X X X X 2000 Mar 15 118 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 101 X-port input reference signal definitions; register set A (92H[3:0]) and B (C2H[3:0]) X = don't care. SAA7114H CONTROL BITS D3 TO D0 X-PORT INPUT REFERENCE SIGNAL DEFINITIONS XCODE XCLK input clock and XDQ input qualifier are needed Data rate is defined by XCLK only, no XDQ signal used Data are qualified at XDQ input at logic 1 Data are qualified at XDQ input at logic 0 Rising edge of XRH input is horizontal reference Falling edge of XRH input is horizontal reference Reference signals are taken from XRH and XRV Reference signals are decoded from EAV and SAV X X X X X X 0 1 XDH X X X X 0 1 X X XDQ X X 0 1 X X X X XCKS 0 1 X X X X X X Table 102 X-port input reference signal definitions; register set A (92H[7:4]) and B (C2H[7:4]) X = don't care. CONTROL BITS D7 TO D4 SCALER INPUT REFERENCE SIGNAL DEFINITIONS XFDV Rising edge of XRV input and decoder V123 is vertical reference Falling edge of XRV input and decoder V123 is vertical reference XRV is a V-sync or V-gate signal XRV is a frame sync, V-pulses are generated internally on both edges of FS input X-port field ID is state of XRH at reference edge on XRV (defined by XFDV) Field ID (decoder and X-port field ID) is inverted Reference edge for field detection is falling edge of XRV Reference edge for field detection is rising edge of XRV X X X X X X 0 1 XFDH X X X X 0 1 X X XDV1 X X 0 1 X X X X XDV0 0 1 X X X X X X 2000 Mar 15 119 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 103 I-port output format and configuration; register set A (93H[4:0]) and B (C3H[4:0]) X = don't care. SAA7114H CONTROL BITS D4 TO D0 I-PORT OUTPUT FORMAT AND CONFIGURATION FOI1 4 : 2 : 2 Dword formatting 4 : 1 : 1 Dword formatting 4 : 2 : 0, only every 2nd line Y + UV output, in between Y only output 4 : 1 : 0, only every 4th line Y + UV output, in between Y only output Y only Not defined Not defined Not defined No leading Y only line, before 1st Y + UV line is output 1 leading Y only line, before 1st Y + UV line is output 2 leading Y only lines, before 1st Y + UV line is output 3 leading Y only lines, before 1st Y + UV line is output X X X X X X X X 0 0 1 1 FOI0 X X X X X X X X 0 1 0 1 FSI2 0 0 0 0 1 1 1 1 X X X X FSI1 0 0 1 1 0 0 1 1 X X X X FSI0 0 1 0 1 0 1 0 1 X X X X Table 104 I-port output format and configuration; register set A (93H[7:5]) and B (C3H[7:5]) X = don't care. CONTROL BITS D7 TO D5 I-PORT OUTPUT FORMAT AND CONFIGURATION ICODE All lines will be output Skip the number of leading Y only lines, as defined by FOI1 and FOI0 Dwords are transferred byte wise, see subaddress 85H bits ISWP1 and ISWP0 Dwords are transferred 16-bit word wise via IPD and HPD, see subaddress 85H bits ISWP1 and ISWP0 No ITU 656 like SAV/EAV codes are available ITU 656 like SAV/EAV codes are inserted in the output data stream, framed by a qualifier X X X X 0 1 I8_16 X X 0 1 X X FYSK 0 1 X X X X 2000 Mar 15 120 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.5.7 SUBADDRESSES 94H TO 9BH SAA7114H Table 105 Horizontal input window start; register set A (94H[7:0]; 95H[3:0]) and B (C4H[7:0]; C5H[3:0]) HORIZONTAL INPUT ACQUISITION WINDOW DEFINITION OFFSET IN X (HORIZONTAL) DIRECTION(1) A minimum of `2' should be kept, due to a line counting mismatch Odd offsets are changing the UV sequence in the output stream to VU sequence Maximum possible pixel offset = 4095 Note 1. Reference for counting are luminance samples. Table 106 Horizontal input window length; register set A (96H[7:0]; 97H[3:0]) and B (C6H[7:0]; C7H[3:0]) HORIZONTAL INPUT ACQUISITION WINDOW DEFINITION INPUT WINDOW LENGTH IN X (HORIZONTAL) DIRECTION(1) No output Odd lengths are allowed, but will be rounded up to even lengths Maximum possible number of input pixels = 4095 Note 1. Reference for counting are luminance samples. Table 107 Vertical input window start; register set A (98H[7:0]; 99H[3:0]) and B (C8H[7:0]; C9H[3:0]) VERTICAL INPUT ACQUISITION WINDOW DEFINITION OFFSET IN Y (VERTICAL) DIRECTION(1) Line offset = 0 Line offset = 1 Maximum line offset = 4095 Note 1. For trigger condition: STRC[1:0]90H[1:0] = 00; YO + YS > (number of input lines per field - 2), will result in field dropping. Other trigger conditions: YO > (number of input lines per field - 2), will result in field dropping. CONTROL BITS A(98H[3:0]) B(C8H[3:0]) A(98H[7:0]) B(C8H[7:0]) CONTROL BITS A (97H[3:0]) B (C7H[3:0]) A(96H[7:0]) B(C6H[7:0]) CONTROL BITS A(95H[3:0]) B(C5H[3:0]) A(94H[7:0]) B(C4H[7:0]) XO11 XO10 XO9 XO8 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 XS11 XS10 XS9 XS8 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 YO11 YO10 YO9 YO8 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 2000 Mar 15 121 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SAA7114H Table 108 Vertical input window length; register set A (9AH[7:0]; 9BH[3:0]) and B (CAH[7:0]; CBH[3:0]) VERTICAL INPUT ACQUISITION WINDOW DEFINITION INPUT WINDOW LENGTH IN Y (VERTICAL) DIRECTION(1) No input lines 1 input line Maximum possible number of input lines = 4095 Note 1. For trigger condition: STRC[1:0]90H[1:0] = 00; YO + YS > (number of input lines per field - 2), will result in field dropping. Other trigger conditions: YS > (number of input lines per field - 2), will result in field dropping. 15.5.8 SUBADDRESSES 9CH TO 9FH CONTROL BITS A(9BH[3:0]) B(CBH[3:0]) YS11 YS10 0 0 1 0 0 1 YS9 0 0 1 YS8 0 0 1 A(9AH[7:0]) B(CAH[7:0]) YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 Table 109 Horizontal output window length; register set A (9CH[7:0]; 9DH[3:0]) and B (CCH[7:0]; CDH[3:0]) HORIZONTAL OUTPUT ACQUISITION WINDOW DEFINITION NUMBER OF DESIRED OUTPUT PIXEL IN X (HORIZONTAL) DIRECTION(1) No output Odd lengths are allowed, but will be filled up to even lengths Maximum possible number of input pixels = 4095; note 2 Notes 1. Reference for counting are luminance samples. 2. If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated. Table 110 Vertical output window length; register set A (9EH[7:0]; 9FH[3:0]) and B (CEH[7:0]; CFH[3:0]) VERTICAL OUTPUT ACQUISITION WINDOW DEFINITION NUMBER OF DESIRED OUTPUT LINES IN Y (VERTICAL) DIRECTION No output 1 pixel Maximum possible number of output lines = 4095; note 1 Note 1. If the desired output length is greater than the number of scaled output lines, the processing is cut. CONTROL BITS A(9FH[3:0]) B(CFH[3:0]) A(9EH[7:0]) B(CEH[7:0]) CONTROL BITS A(9DH[3:0]) B(CDH[3:0]) A(9CH[7:0]) B(CCH[7:0]) XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 2000 Mar 15 122 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.5.9 SUBADDRESSES A0H TO A2H SAA7114H Table 111 Horizontal prescaling; register set A (A0H[5:0]) and B (D0H[5:0]) CONTROL BITS D5 TO D0 HORIZONTAL INTEGER PRESCALING RATIO (XPSC) XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0 Not allowed Down-scale = 1 Down-scale = ... Down-scale = 163 1 2 0 0 0 ... 1 0 0 0 ... 1 0 0 0 ... 1 0 0 0 ... 1 0 0 1 ... 1 0 1 0 ... 1 Table 112 Accumulation length; register set A (A1H[5:0]) and B (D1H[5:0]) HORIZONTAL PRESCALER ACCUMULATION SEQUENCE LENGTH (XACL) Accumulation length = 1 Accumulation length = 2 ... Accumulation length = 64 CONTROL BITS D5 TO D0 XACL5 XACL4 XACL3 XACL2 XACL1 XACL0 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 1 ... 1 Table 113 Prescaler DC gain and FIR prefilter control; register set A (A2H[3:0]) and B (D2H[3:0]) X = don't care. CONTROL BITS D3 TO D0 PRESCALER DC GAIN XC2_1 Prescaler output is renormalized by gain factor = 1 Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = 1 1 1 1 1 2 XDCG2 0 0 0 0 1 1 1 1 X X XDCG1 0 0 1 1 0 0 1 1 X X XDCG0 0 1 0 1 0 1 0 1 X X X X X X X X X X 0 1 Prescaler output is renormalized by gain factor = 14 8 16 Prescaler output is renormalized by gain factor = 132 64 128 Weighting of all accumulated samples is factor `1'; e.g. XACL = 4 sequence 1 + 1 + 1 + 1 + 1 Weighting of samples inside sequence is factor `2'; e.g. XACL = 4 sequence 1 + 2 + 2 + 2 + 1 2000 Mar 15 123 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 114 Prescaler DC gain and FIR prefilter control; register set A (A2H[7:4]) and B (D2H[7:4]) X = don't care. SAA7114H CONTROL BITS D7 TO D4 FIR PREFILTER CONTROL PFUV1 Luminance FIR filter bypassed H_y(z) = H_y(z) = H_y(z) = 1 (1 2 1) 4 1 (-1 1 1.75 4.5 8 1 (1 2 2 2 1) 8 PFUV0 X X X X 0 1 0 1 PFY1 0 0 1 1 X X X X PFY0 0 1 0 1 X X X X X X X X 0 0 1 1 1.75 1 -1) Chrominance FIR filter bypassed H_uv(z) = 14(1 2 1) H_uv(z) = 132(3 8 10 8 3) H_uv(z) = 1 8(1 2 2 2 1) 15.5.10 SUBADDRESSES A4H TO A6H Table 115 Luminance brightness setting; register set A (A4H[7:0]) and B (D4H[7:0]) LUMINANCE BRIGHTNESS SETTING Value = 0 Nominal value = 128 Value = 255 CONTROL BITS D7 TO D0 BRIG7 0 1 1 BRIG6 0 0 1 BRIG5 0 0 1 BRIG4 0 0 1 BRIG3 0 0 1 BRIG2 0 0 1 BRIG1 0 0 1 BRIG0 0 0 1 Table 116 Luminance contrast setting; register set A (A5H[7:0]) and B (D5H[7:0]) LUMINANCE CONTRAST SETTING Gain = 0 Gain = 1 64 CONTROL BITS D7 TO D0 CONT7 0 0 0 0 CONT6 0 0 1 1 CONT5 0 0 0 1 CONT4 0 0 0 1 CONT3 0 0 0 1 CONT2 0 0 0 1 CONT1 0 0 0 1 CONT0 0 1 0 1 Nominal gain = 64 Gain = 12764 Table 117 Chrominance saturation setting; register set A (A6H[7:0]) and B (D6H[7:0]) CHROMINANCE SATURATION SETTING Gain = 0 Gain = Gain = 1 64 CONTROL BITS D7 TO D0 SATN7 0 0 0 0 SATN6 0 0 1 1 SATN5 0 0 0 1 SATN4 0 0 0 1 SATN3 0 0 0 1 SATN2 0 0 0 1 SATN1 0 0 0 1 SATN0 0 1 0 1 Nominal gain = 64 127 64 2000 Mar 15 124 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.5.11 SUBADDRESSES A8H TO AEH SAA7114H Table 118 Horizontal luminance scaling increment; register set A (A8H[7:0]; A9H[7:0]) and B (D8H[7:0]; D9H[7:0]) CONTROL BITS HORIZONTAL LUMINANCE SCALING INCREMENT 1024 (theoretical) zoom 1 1024 294, lower limit defined A(A9H[7:4]) B(D9H[7:4]) XSCY[15:12] A(A9H[3:0]) B(D9H[3:0]) XSCY[11:8] 0000 0001 0011 0100 0100 1111 A(A8H[7:4]) B(D8H[7:4]) XSCY[7:4] 0000 0010 1111 0000 0000 1111 A(A8H[3:0]) B(D8H[3:0]) XSCY[3:0] 0000 0110 1111 0000 0001 1111 Scale = 0000 by 0000 0000 0000 0000 0001 Scale = data path structure Scale = 10241023 zoom Scale = 1, equals 1024 Scale = 10241025 down-scale Scale = 1024 8191 down-scale Table 119 Horizontal luminance phase offset; register set A (AAH[7:0]) and B (DAH[7:0]) HORIZONTAL LUMINANCE PHASE OFFSET Offset = 0 Offset = Offset = Offset = 1 pixel 32 32 = 1 pixel 32 255 pixel 32 CONTROL BITS D7 TO D0 XPHY7 0 0 0 1 XPHY6 0 0 0 1 XPHY5 0 0 1 1 XPHY4 0 0 0 1 XPHY3 0 0 0 1 XPHY2 0 0 0 1 XPHY1 0 0 0 1 XPHY0 0 1 0 1 Table 120 Horizontal chrominance scaling increment; register set A (ACH[7:0]; ADH[7:0]) and B (DCH[7:0]; DDH[7:0]) CONTROL BITS HORIZONTAL CHROMINANCE SCALING INCREMENT A (ADH[7:4]) B (DDH[7:4]) XSCC[15:12](1) This value must be set to the luminance value 12XSCY[15:0] 0000 0000 0001 Note 1. Bits XSCC[15:13] are reserved and are set to logic 0. Table 121 Horizontal chrominance phase offset; register set A (AEH[7:0]) and B (DEH[7:0]) HORIZONTAL CHROMINANCE PHASE OFFSET This value must be set to 1 XPHY[7:0] 2 A (ADH[3:0]) B (DDH[3:0]) XSCC[11:8] 0000 0000 1111 A (ACH[7:4]) B (DCH[7:4]) XSCC[7:4] 0000 0000 1111 A (ACH[3:0]) B (DCH[3:0]) XSCC[3:0] 0000 0001 1111 CONTROL BITS D7 TO D0 XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 2000 Mar 15 125 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 15.5.12 SUBADDRESSES B0H TO BFH SAA7114H Table 122 Vertical luminance scaling increment; register set A (B0H[7:0]; B1H[7:0]) and B (E0H[7:0]; E1H[7:0]) CONTROL BITS VERTICAL LUMINANCE SCALING INCREMENT 1024 (theoretical) 1 1024 1023 zoom A (B1H[7:4]) B (E1H[7:4]) YSCY[15:12] A (B1H[3:0]) B (E1H[3:0]) YSCY[11:8] 0000 0011 0100 0100 1111 A (B0H[7:4]) B (E0H[7:4]) YSCY[7:4] 0000 1111 0000 0000 1111 A (B0H[3:0]) B (E0H[3:0]) YSCY[3:0] 0001 1111 0000 0001 1111 Scale = Scale = Scale = Scale = zoom 0000 0000 0000 0000 1111 Scale = 1, equals 1024 1024 1025 down-scale 1 63.999 down-scale Table 123 Vertical chrominance scaling increment; register set A (B2H[7:0]; B3H[7:0]) and B (E2H[7:0]; E3H[7:0]) CONTROL BITS VERTICAL CHROMINANCE SCALING INCREMENT A (B3H[7:4]) B (E3H[7:4]) YSCC[15:12] This value must be set to the luminance value YSCY[15:0] 0000 1111 A (B3H[3:0]) B (E3H[3:0]) YSCC[11:8] 0000 1111 A (B2H[7:4]) B (E2H[7:4]) YSCC[7:4] 0000 1111 A (B2H[3:0]) B (E2H[3:0]) YSCC[3:0] 0001 1111 Table 124 Vertical scaling mode control; register set A (B4H[4 and 0]) and B (E4H[4 and 0]) X = don't care. CONTROL BITS D4 AND D0 VERTICAL SCALING MODE CONTROL YMIR Vertical scaling performs linear interpolation between lines Vertical scaling performs higher order accumulating interpolation, better alias suppression No mirroring Lines are mirrored X X 0 1 YMODE 0 1 X X Table 125 Vertical chrominance phase offset `00'; register set A (B8H[7:0]) and B (E8H[7:0]) VERTICAL CHROMINANCE PHASE OFFSET Offset = 0 Offset = 32 32 CONTROL BITS D7 TO D0 YPC07 0 0 1 YPC06 0 0 1 YPC05 0 1 1 YPC04 0 0 1 YPC03 0 0 1 YPC02 0 0 1 YPC01 0 0 1 YPC00 0 0 1 = 1 line Offset = 25532 lines 2000 Mar 15 126 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 126 Vertical luminance phase offset `00'; register set A (BCH[7:0]) and B (ECH[7:0]) VERTICAL LUMINANCE PHASE OFFSET Offset = 0 Offset = 3232 = 1 line Offset = 25532 lines 16 PROGRAMMING START SET-UP 16.1 Decoder part CONTROL BITS D7 TO D0 YPY07 0 0 1 YPY06 0 0 1 YPY05 0 1 1 YPY04 0 0 1 YPY03 0 0 1 YPY02 0 0 1 SAA7114H YPY01 0 0 1 YPY00 0 0 1 The given values force the following behaviour of the SAA7114H decoder part: * The analog input AI11 expects an NTSC M, PAL BDGHI or SECAM signal in CVBS format; analog anti-alias filter and AGC active * Automatic field detection enabled * Standard ITU 656 output format enabled on expansion (X) port * Contrast, brightness and saturation control in accordance with ITU standards * Adaptive comb filter for luminance and chrominance activated * Pins LLC, LLC2, XTOUT, RTS0, RTS1 and RTCO are set to 3-state. Table 127 Decoder part start set-up values for the three main standards SUB ADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C REGISTER FUNCTION chip version horizontal increment delay analog input control 1 analog input control 2 analog input control 3 analog input control 4 horizontal sync start horizontal sync stop sync control luminance control luminance brightness control luminance contrast control chrominance saturation control ID07 to ID04 X, X, X, X, IDEL3 to IDEL0 FUSE1 and FUSE0, GUDL1 to GUDL0, MODE3 to MODE0 X, HLNRS, VBSL, WPOFF, HOLDG, GAFIX, GAI28 and GAI18 GAI17 to GAI10 GAI27 to GAI20 HSB7 to HSB0 HSS7 to HSS0 AUFD, FSEL, FOET, HTC1, HTC0, HPLL, VNOI1 and VNOI0 BYPS, YCOMB, LDEL, LUBW, LUFI3 to LUFI0 DBRI7 to DBRI0 DCON7 to DCON0 DSAT7 to DSAT0 08 C0 10 90 90 EB E0 98 40 80 44 40 VALUES (HEX) BIT NAME(1) NTSC M PAL BDGHI SECAM read only 08 C0 10 90 90 EB E0 98 40 80 44 40 08 C0 10 90 90 EB E0 98 1B 80 44 40 2000 Mar 15 127 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler SUB ADDRESS (HEX) 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A to 1E 1F Note 1. All X values must be set to LOW. REGISTER FUNCTION chrominance hue control chrominance control 1 chrominance gain control chrominance control 2 mode/delay control RT signal control RT/X-port output control analog, ADC, compatibility control VGATE start, FID change VGATE stop miscellaneous/VGATE MSBs raw data gain raw data offset reserved decoder status byte (OLDSB = 0) SAA7114H VALUES (HEX) BIT NAME(1) NTSC M PAL BDGHI SECAM HUEC7 to HUEC0 CDTO, CSTD2 to CSTD0, DCVF, FCTC, X, CCOMB ACGC, CGAIN6 to CGAIN0 OFFU1, OFFU0, OFFV1, OFFV0, CHBW, LCBW2 to LCBW0 COLO, RTP1, HDEL1, HDEL0, RTP0, YDEL2 to YDEL0 RTSE13 to RTSE10, RTSE03 to RTSE00 RTCE, XRHS, XRVS1, XRVS0, HLSEL, OFTS2 to OFTS0 CM99, UPTCV, AOSL1, AOSL0, XTOUTE, OLDSB, APCK1 and APCK0 VSTA7 to VSTA0 VSTO7 to VSTO0 LLCE, LLC2E, X, X, X, VGPS, VSTO8 and VSTA8 RAWG7 to RAWG0 RAWO7 to RAWO0 X, X, X, X, X, X, X, X INTL, HVLN, FIDT, GLIMT, GLIMB, WIPA, COPRO, RDCAP 00 89 2A 0E 00 00 00 00 11 FE 40 40 80 00 00 81 2A 06 00 00 00 00 11 FE 40 40 80 00 read only 00 D0 80 00 00 00 00 00 11 FE 40 40 80 00 2000 Mar 15 128 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 16.2 Audio clock generation part SAA7114H The given values force the following behaviour of the SAA7114H audio clock generation part: * Used crystal is 24.576 MHz * Expected field frequency is 59.94 Hz (e.g. NTSC M standard) * Generated audio master clock frequency at pin AMCLK is 256 x 44.1 kHz = 11.2896 MHz * AMCLK is externally connected to AMXCLK (short-cut between pins 37 and 41) * ASCLK = 32 x 44.1 kHz = 1.4112 MHz * ALRCLK is 44.1 kHz. Table 128 Audio clock part set-up values SUB ADDRESS (HEX) 30 31 32 33 34 35 36 37 38 39 3A 3B to 3F Note 1. All X values must be set to LOW. START VALUES REGISTER FUNCTION audio master clock cycles per field; bits 7 to 0 audio master clock cycles per field; bits 15 to 8 audio master clock cycles per field; bits 17 and 16 reserved audio master clock nominal increment; bits 7 to 0 audio master clock nominal increment; bits 15 to 8 audio master clock nominal increment; bits 21 to 16 reserved clock ratio AMXCLK to ASCLK clock ratio ASCLK to ALRCLK audio clock generator basic set-up reserved BIT NAME(1) 7 6 5 4 3 2 1 0 HEX ACPF7 to ACPF0 ACPF15 to ACPF8 10111100 11011111 BC DF 02 00 CD CC 3A 00 03 10 00 00 X, X, X, X, X, X, ACPF17 and ACPF16 0 0 0 0 0 0 1 0 X, X, X, X, X, X, X, X ACNI7 to ACNI0 ACNI15 to ACNI8 X, X, ACNI21 to ACNI16 X, X, X, X, X, X, X, X X, X, SDIV5 to SDIV0 X, X, LRDIV5 to LRDIV0 X, X, X, X, APLL, AMVR, LRPH, SCPH X, X, X, X, X, X, X, X 00000000 11001101 11001100 00111010 00000000 00000011 00010000 00000000 00000000 2000 Mar 15 129 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 16.3 Data slicer and data type control part SAA7114H The given values force the following behaviour of the SAA7114H VBI-data slicer part: * Closed captioning data are expected at line 21 of field 1 (60 Hz/525 line system) * All other lines are processed as active video * Sliced data are framed by ITU 656 like SAV/EAV sequence (DID[5:0] = 3EH MSB of SAV/EAV = 1). Table 129 Data slicer start set-up values SUB ADDRESS (HEX) 40 41 to 53 54 55 to 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 Notes 1. All X values must be set to LOW. 2. Changes for 50 Hz/625 line systems: subaddress 5AH = 03H and subaddress 5BH = 03H. START VALUES FUNCTION slicer control 1 line control register 2 to 20 line control register 21 line control register 22 to 24 programmable framing code horizontal offset for slicer vertical offset for slicer field offset and MSBs for horizontal and vertical offset reserved header and data identification code control sliced data identification code reserved slicer status byte 1 slicer status byte 2 BIT NAME(1) 7 6 5 4 3 2 1 0 HEX X, HAM_N, FCE, HUNT_N, X, X, X, X LCRn_7 to LCRn_0 (n = 2 to 20) LCR21_7 to LCR21_0 LCRn_7 to LCRn_0 (n = 22 to 24) FC7 to FC0 HOFF7 to HOFF0 VOFF7 to VOFF0 FOFF, RECODE, X, VOFF8, X, HOFF10 to HOFF8 X, X, X, X, X, X, X, X FVREF, X, DID5 to DID0 X, X, SDID5 to SDID0 X, X, X, X, X, X, X, X -, FC8V, FC7V, VPSV, PPV, CCV, -, - -, -, F21_N, LN8 to LN4 LN3 to LN0, DT3 to DT0 01000000 11111111 01011111 11111111 00000000 01000111 00 FF 5F FF 00 47 0 0 0 0 0 1 1 0 06(2) 1 0 0 0 0 0 1 1 83(2) 00000000 00111110 00000000 00000000 read-only register read-only register read-only register 00 3E 00 00 2000 Mar 15 130 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 16.4 Scaler and interfaces 16.4.1 TRIGGER CONDITION SAA7114H Table 130 shows some examples for the scaler programming with: * prsc = prescale ratio * fisc = fine scale ratio * vsc = vertical scale ratio. number of input pixel The ratio is defined as: ---------------------------------------------------------number of output pixel In the following settings the VBI-data slicer is inactive. To activate the VBI-data slicer, VITX[1:0]86H[7:6] has to be set to `11'. Dependent on the VBI-data slicer settings, the sliced VBI-data are inserted after end of scaled video lines, if the regions of VBI-data slicer and scaler overlaps. To compensate the running-in of the vertical scaler, the vertical input window lengths are extended by 2 to 290 lines, respectively 242 lines for XS, but the scaler increment calculations are done with 288, respectively 240 lines. 16.4.3 EXAMPLES For trigger condition STRC[1:0]90H[1:0] not equal `00'. If the value of (YO + YS) is greater equal 262 (NTSC), respectively 312 (PAL) the output field rate is reduced to 30 Hz, respectively 25 Hz. Horizontal and vertical offsets (XO and YO) have to be used to adjust the displayed video in the display window. As this adjustment is application dependent, the listed values are only dummy values. 16.4.2 MAXIMUM ZOOM FACTOR The maximum zoom factor is dependent on the back-end data rate and therefore back-end clock and data format dependent (8 or 16-bit output). The maximum horizontal zoom is limited to about 3.5, due to internal data path restrictions. Table 130 Example configurations EXAMPLE NUMBER 1 SCALER SOURCE AND REFERENCE EVENTS analog input to 8-bit I-port output, with SAV/EAV codes, 8-bit serial byte stream decoder output at X-port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; H and V-gates on IGPH and IGPV, IGP0 = VBI sliced data flag, IGP1 = FIFO almost full, level 24, IDQ qualifier logic 1 active analog input to 16-bit output, without SAV/EAV codes, Y on I-port, UV on H-port and decoder output at X-port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; H and V-pulses on IGPH and IGPV, output FID on IGP0, IGP1 fixed to logic 1, IDQ qualifier logic 0 active X-port input 8 bit with SAV/EAV codes, no reference signals on XRH and XRV, XCLK as gated clock; field detection and acquisition trigger on different events; acquisition triggers at rising edge vertical and rising edge horizontal; I-port output 8 bit with SAV/EAV codes like example number 1 X-port and H-port for 16-bit YUV 4 : 2 : 2 input (if no 16-bit output selected); XRH and XRV as references; field detection and acquisition trigger at falling edge vertical and rising edge horizontal; I-port output 8 bit with SAV/EAV codes, but Y only output INPUT OUTPUT WINDOW WINDOW SCALE RATIOS 720 x 240 720 x 240 prsc = 1; fisc = 1; vsc = 1 2 704 x 288 768 x 288 prsc = 1; fisc = 0.91667; vsc = 1 3 720 x 240 352 x 288 prsc = 2; fisc = 1.022; vsc = 0.8333 4 720 x 288 200 x 80 prsc = 2; fisc = 1.8; vsc = 3.6 2000 Mar 15 131 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler Table 131 Scaler and interface configuration example I2C-BUS ADDRESS (HEX) Global settings 80 83 84 85 86 87 88 task enable, IDQ and back-end clock definition XCLK output phase and X-port output enable IGPH, IGPV, IGP0 and IGP1 output definition signal polarity control and I-port byte swapping FIFO flag thresholds and video/text arbitration ICLK and IDQ output phase and I-port enable power save control and software reset 10 01 A0 10 45 01 F0 - - - - - - - - - - - 16 - 720 - 10 - 242 - 720 - 240 - - - - 128 64 64 10 01 C5 09 40 01 F0 - - - - - - - - - - - 16 - 704 - 10 - 290 - 768 - 288 - - - - 128 64 64 10 00 A0 10 45 01 F0 SAA7114H EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4 MAIN FUNCTIONALITY HEX DEC HEX DEC HEX DEC HEX DEC - - - - - - - - - - - 16 - 720 - 10 - 242 - 352 - 288 - - - - 128 64 64 10 00 A0 10 45 01 F0 - - - - - - - - - - - 16 - 720 - 10 - 290 - 200 - 80 - - - - 128 17 17 Task A: scaler input configuration and output format settings 90 91 92 93 task handling scaler input source and format definition reference signal definition at scaler input I-port output formats and configuration 00 08 10 80 00 08 10 40 00 18 10 80 00 38 10 84 Input and output window definition 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F horizontal output (destination) window length (XD) vertical output (destination) window length (YD) vertical input (source) window length (YS) vertical input offset (YO) horizontal input (source) window length (XS) horizontal input offset (XO) 10 00 D0 02 0A 00 F2 00 D0 02 F0 00 10 00 C0 02 0A 00 22 01 00 03 20 01 10 00 D0 02 0A 00 F2 00 60 01 20 01 10 00 D0 02 0A 00 22 01 C8 00 50 00 Prefiltering and prescaling A0 A1 A2 A4 A5 A6 integer prescale (value `00' not allowed) accumulation length for prescaler FIR prefilter and prescaler DC normalization scaler brightness control scaler contrast control scaler saturation control 01 00 00 80 40 40 01 00 00 80 40 40 02 02 AA 80 40 40 02 03 F2 80 11 11 2000 Mar 15 132 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler I2C-BUS ADDRESS (HEX) SAA7114H EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4 MAIN FUNCTIONALITY HEX DEC HEX DEC HEX DEC HEX DEC Horizontal phase scaling A8 A9 AA AC AD AE horizontal phase offset chrominance Vertical scaling B0 B1 B2 B3 B4 B8 to BF vertical scaling mode control vertical phase offsets luminance and chrominance (need to be used for interlace correct scaled output) vertical scaling increment for chrominance vertical scaling increment for luminance 00 04 00 04 00 1024 - 1024 - - 00 04 00 04 00 1024 - 1024 - - 55 03 55 03 00 853 - 853 - - 66 0E 66 0E 01 3686 - 3686 - - horizontal phase offset luminance horizontal scaling increment for chrominance horizontal scaling increment for luminance 00 04 00 00 02 00 1024 - - 512 - - AA 03 00 D5 01 00 938 - - 469 - - 18 04 00 0C 02 00 1048 - - 524 - - 34 07 00 9A 03 00 1844 - - 922 - - start with B8 to BF at 00H, if there are no problems with the interlaced scaled output optimize according to Section 8.3.3.2 2000 Mar 15 133 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 17 PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SAA7114H SOT407-1 c y X 75 76 51 50 ZE A e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X Lp A A2 (A 3) A1 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o o 16.25 16.25 15.75 15.75 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 EIAJ EUROPEAN PROJECTION ISSUE DATE 00-01-19 00-02-01 2000 Mar 15 134 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 18 SOLDERING 18.1 Introduction to soldering surface mount packages SAA7114H * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 18.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 18.3 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 2000 Mar 15 135 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 18.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable suitable suitable suitable suitable suitable SAA7114H REFLOW(1) 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Mar 15 136 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler 19 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values SAA7114H This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2000 Mar 15 137 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler NOTES SAA7114H 2000 Mar 15 138 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler NOTES SAA7114H 2000 Mar 15 139 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000 Internet: http://www.semiconductors.philips.com SCA 69 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753505/01/pp140 Date of release: 2000 Mar 15 Document order number: 9397 750 05976 |
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